A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Mahadevan, Shankar; Angiolini, Federico; Storgaard, Michael; Olsen, Rasmus Grondahl; Sparsø, Jens; Madsen, Jan

doi:10.1109/date.2005.22

Cited by 41 publications

(21 citation statements)

References 9 publications

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“…Each unit is designed as a Bus Functional Model (BFM) based on SystemC [6]. We designed the BFM considering the delay time of each of the blocks, and it generates communication traffics in a specific simulation environments.…”

Section: Simulation Resultsmentioning

confidence: 99%

A Low-Cost Standard Mode MPI Hardware Unit for Embedded MPSoC

Chung

Jeong

et al. 2011

IEICE Trans. Inf. & Syst.

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Won-young CHUNG†a) , Student Member, Ha-young JEONG † , Won Woo RO †b) , and Yong-surk LEE †c) , Nonmembers SUMMARYIn this paper, we propose a novel low-cost Message Passing Interface (MPI) unit between processor nodes, which supports message passing in multiprocessor systems using distributed memory architecture. Our MPI unit operates in the standard mode -using the buffered mode for small amounts of data transaction and the synchronous mode for large amounts of data transaction. This results in increased performance by reducing the control message transmission time for the small amount of data. We verified the performance with a simulator designed based on SystemC. Additionally, we designed the MPI unit using VerilogHDL, and we synthesized it with a synopsys design compiler. The proposed standard mode MPI unit shows a high performance even though the size of the MPI unit occupies less than 1 % of the whole chip. Thus, with respect to low-cost design and scalability, this MPI hardware unit is useful to increase overall performance of the embedded Multiprocessor System on a Chip (MPSoC).

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Section: Simulation Resultsmentioning

confidence: 99%

A Low-Cost Standard Mode MPI Hardware Unit for Embedded MPSoC

Chung

Jeong

et al. 2011

IEICE Trans. Inf. & Syst.

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“…More specifically related to on-chip traffic generation, two main approaches have been studied: deterministic traffic generation, in which the objective is to exactly reproduce the traffic of a given ip [13,19,20] and stochastic traffic generation which uses random sources in place of real ips [17,25,31]. In the deterministic approach, Mahadevan et al introduced, for instance, a trace compiler able to accurately reproduce the traffic of a processor [20]. As networks on chip are still in early stages of development, the main part of their performance evaluation is done using a random source.…”

Section: Related Workmentioning

confidence: 99%

Long-range dependence and on-chip processor traffic

Scherrer

Fraboulet

Risset

2009

Microprocessors and Microsystems

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Long-range dependence is a property of stochastic processes that has an important impact on network performance, especially on the buffer usage in routers. We analyze the presence of long-range dependence in on-chip processor traffic and we study the impact of long-range dependence on networks-on-chip. We propose to investigate the presence of long-range dependence in communication traces of processor ips at the cycle-accurate level. We also study the impact of long-range dependence on a real network-on-chip using the SocLib simulation environment and traffic generators of our own. Our experiments show that long-range dependence is not an ubiquitous property of on-chip processor traffic and that its impact on the network-on-chip is highly correlated with the low level communication protocol used.

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“…One possibility ( Fig. 1) is to leverage its features to replace existing IP cores; this usage has previously been introduced in [5] and [23]. The idea is to accurately reproduce communication transactions based on prerecorded system traces.…”

Section: Introductionmentioning

confidence: 99%

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

Mahadevan

Angiolini

Sparsø

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bitand cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (tasksynchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context.

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A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Cited by 41 publications

References 9 publications

A Low-Cost Standard Mode MPI Hardware Unit for Embedded MPSoC

A Low-Cost Standard Mode MPI Hardware Unit for Embedded MPSoC

Long-range dependence and on-chip processor traffic

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

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