A neuromorphic hardware framework based on population coding

Thakur, Chetan Singh; Hamilton, Tara Julia; Wang, Runchun; Tapson, Jonathan; Schaik, André van

doi:10.1109/ijcnn.2015.7280591

Cited by 20 publications

(12 citation statements)

References 32 publications

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“…However, our approach does not require high voltages for programming floating-gates and is also much more compact due to the use of only one transistor without capacitors in the multiplier cell. [28] also uses random mismatch (and a systematic offset) in 65nm CMOS to perform the calculations in the first stage of ELM. However, they only have a single dimensional input and only show regression.…”

Section: E Comparisonmentioning

confidence: 99%

VLSI Extreme Learning Machine: A Design Space Exploration

Yao

Basu

2017

IEEE Trans. VLSI Syst.

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In this paper, we describe a compact low-power high-performance hardware implementation of extreme learning machine for machine learning applications. Mismatches in current mirrors are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. Both regression and classification (on UCI data sets) are demonstrated and a design space tradeoff between speed, power, and accuracy is explored. Our results indicate that for a wide set of problems, σ V T in the range of 15-25 mV gives optimal results. An input weight matrix rotation method to extend the input dimension and hidden layer size beyond the physical limits imposed by the chip is also described. This allows us to overcome a major limit imposed on most hardware machine learners. The chip is implemented in a 0.35-μm CMOS process and occupies a die area of around 5 mm × 5 mm. Operating from a 1 V power supply, it achieves an energy efficiency of 0.47 pJ/MAC at a classification rate of 31.6 kHz.Index Terms-Classifier, extreme learning machine (ELM), low power, machine learning, neural networks. 1063-8210Enyi Yao received the B.Eng. degree from the Harbin Institute of Technology, Harbin, China, in 2011. He is currently pursuing the Ph.D. degree in electrical and electronic engineering with the Nanyang Technological University, Singapore.His current research interests include low power analog, mixed-signal IC design, neuromorphic circuits design, and low power smart sensor circuits design for biomedical applications.Arindam Basu received the B.Tech. and M.Tech.

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Section: E Comparisonmentioning

confidence: 99%

VLSI Extreme Learning Machine: A Design Space Exploration

Yao

Basu

2017

IEEE Trans. VLSI Syst.

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“…Biological real-time neuromorphic system has been found in [110]. Population coding of neural activity has been done using a Trainable Analogue Block approach by Thakur et al [111].…”

Section: Applications In Biomedical and Biosignal Engineeringmentioning

confidence: 99%

Recent trends in neuromorphic engineering

Soman

Jayadeva

2016

Big Data Anal

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Neuromorphic Engineering has emerged as an exciting research area, primarily owing to the paradigm shift from conventional computing architectures to data-driven, cognitive computing. There is a diversity of work in the literature pertaining to neuromorphic systems, devices and circuits. This review looks at recent trends in neuromorphic engineering and its sub-domains, with an attempt to identify key research directions that would assume significance in the future. We hope that this review would serve as a handy reference to both beginners and experts, and provide a glimpse into the broad spectrum of applications of neuromorphic hardware and algorithms. Our survey indicates that neuromorphic engineering holds a promising future, particularly with growing data volumes, and the imminent need for intelligent, versatile computing.

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“…There are several reported hardware architectures exploiting randomness in VLSI for ELM [15][16][17]. Of these, [15] shows the application of ELM to a single input single output regression problem. On the other hand, [16,17] have already shown good accuracy at the system level for applications like intention decoding [17] and spike sorting [16] requiring multiple inputs and outputshence, we pursue this architecture further.…”

Section: Introductionmentioning

confidence: 99%

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

et al. 2017

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We demonstrate a low-power and compact hardware implementation of Random Feature Extractor (RFE) core. With complex tasks like Image Recognition requiring a large set of features, we show how weight reuse technique can allow to virtually expand the random features available from RFE core. Further, we show how to avoid computation cost wasted for propagating "incognizant" or redundant random features. For proof of concept, we validated our approach by using our RFE core as the first stage of Extreme Learning Machine (ELM)-a two layer neural network-and were able to achieve > 97% accuracy on MNIST database of handwritten digits. ELM's first stage of RFE is done on an analog ASIC occupying 5mm×5mm area in 0.35µm CMOS and consuming 5.95 µJ/classify while using ≈ 5000 effective hidden neurons. The ELM second stage consisting of just adders can be implemented as digital circuit with estimated power consumption of 20.9 nJ/classify. With a total energy consumption of only 5.97 µJ/classify, this low-power mixed signal ASIC can act as a co-processor in portable electronic gadgets with cameras.

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A neuromorphic hardware framework based on population coding

Cited by 20 publications

References 32 publications

VLSI Extreme Learning Machine: A Design Space Exploration

VLSI Extreme Learning Machine: A Design Space Exploration

Recent trends in neuromorphic engineering

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

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