A new approach to protect FPGA based sequential IP cores

Abstract

Protection of Intellectual property (IP) cores plays an important role in the EDA industry because a large amount of money is invested in designing IP core. IP vendors are facing major challenge to protect IPs and to prevent revenue loss due to IP piracy. In this paper a new dynamic watermarking scheme is proposed. The watermark is embedded in the state transitions of FSM at the behavioural level. A watermark is embedded into FSM by hierarchically splitting original FSM into smaller FSMs. Experimental results on IWLS93 benchmarks shows that the watermarking technique is a secure and robust method for protecting IP cores represented in FSM.