A new approach to switch fabrics based on mini-router grids and output queueing

2017

Computer Networks

Data Center switches need guarantee high throughput, resiliency and scalability for large-scale networks with constantly floating requirements. Multistage packet switches have been a pervasive solution to implement high-capacity Data Center Networks (DCNs) switches and routers. Yet, classical multistage switching architectures with their Space-Memory variants have shown limited performance. Most proposals prove either too complex to implement or not cost effective. In this paper, we present a highly scalable packet-switch for the DCN environment, in which we exploit the Network-on-Chip (NoC) design paradigm to replace the single-hop crossbars with multi-hop Switching Elements (SEs). In particular, we describe a three-stage switch with Output-Queued Unidirectional NoCs (OQ-UDN) in the central stage of the Clos-network. The design has several advantages over conventional multistage switches. First, it uses a simple Round-Robin (RR) packet dispatching scheme and avoids the need for complex and costly input modules. Besides, it offers better load balancing, a pipelined scheduling and more path-diversity. We assess the performance of the switch in terms of throughput, end-to-end latency and blocking probability using Markov chain analysis, and we propose an analytical model that integrates the various design parameters. Through extensive simulations, we show that the switching architecture achieves high performance under different types of traffic, and that both the analytical and experimental results correlate over wide range of evaluation settings.

Section: Related Workmentioning

confidence: 96%

A scalable packet-switch architecture based on OQ NoCs for data center networks

2017

Computer Networks

“…Another approach based on G/G/1 queues and priority queues is presented in [11] to estimate the latency in the network. In 2015, Karadeniz et al presented a low-complexity model for single-stage switch based on Network-on-Chip and OQ routers [4]. This paper suggests analytical models for the throughput and blocking probability of the OQ Clos-UDN switch.…”

Section: Related Workmentioning

confidence: 99%

“…As represented in Fig. 1 can be general 4 , the proposed OQ Clos-UDN architecture has an expansion factor m n = 1, making it a Benes lowest-cost practical non-blocking fabric. An IM(i ) has m FIFOs each of which is associated to one of the m output links denoted as LI(i , r ).…”

Section: A Terminology Of the Switch Architecturementioning

confidence: 99%

Providing performance guarantees in data center network switching fabrics

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)

2016

Abstract-This paper proposes a novel and highly scalable multistage packet-switch design based on Networks-on-Chip (NoC). In particular, we describe a three-stage Clos packet-switch fabric with a Round-Robin packets dispatching scheme where each central stage module is an Output-Queued Unidirectional NoC (OQ-UDN), instead of the conventional single-hop crossbar. We test the switch performance under different traffic profiles. In addition to experimental results, we present an analytical approximation for the theoretical throughput of the switch under Bernoulli i.i.d arrivals. We also provide an upper-bound estimation of the end-to-end blocking probability in the proposed switch to help predict performance and to optimize the design.

“…The OQ-UDN switch with small output queues and internal back-pressure control offers lower cost than fabrics with large internal buffers. Although in a MR of degree n, all output ports must run n times faster than an input port to handle the worst case scenario, the required internal speedup is bounded to 3 and the hardware implementation of the module is feasible [13]. Given the technology advance, on-chip logic and memory VLSI implementation costs much less than off-chip communication.…”

Section: Routing In the Oq-udn Modulesmentioning

confidence: 99%

“…Unlike with IQ-UDN modules [7] where every onchip router selects packets in a RR manner to forward them to the next hop making the complexity equals to O(log kM ), OQ-UDN is fitted with output queues that absorb traffic with respect to their capacity. In [13], authors discuss a possible HW implementation of a single-stage WUDN packet switch that is quite similar to the OQ-UDN. The implementation of a module is perfectly feasible considering the current technology whereby cost/performance trade-off is made by varying the switch parameters and/or the synthesis technology.…”

Section: B Hardware Requirementsmentioning

confidence: 99%

A scalable packet-switch based on output-queued NoCs for data centre networks

2016 IEEE International Conference on Communications (ICC)

2016

Abstract-The switch fabric in a Data-Center Network (DCN) handles constantly variable loads. This is stressing the need for high-performance packet switches able to keep pace with climbing throughput while maintaining resiliency and scalability. Conventional multistage switches with their space-memory variants proved to be performance limited as they do not scale well with the proliferating DC requirements. Most proposals are either too complex to implement or not cost effective. In this paper, we present a highly scalable multistage switching architecture for DC switching fabrics. We describe a three-stage Clos packet-switch fabric with Output-Queued Unidirectional NoC (OQ-UDN) modules and Round-Robin packets dispatching scheme. The proposed OQ Clos-UDN architecture avoids the need for complex and costly input modules and simplifies the scheduling process. Thanks to a dynamic packets dispatching and the multi-hop nature of the UDN modules, the switch provides load balancing and path-diversity. We compared our proposed architecture to state-of-the art previous architectures under extensive uniform and non-uniform DC traffic types. Simulations of various switch settings have shown that the proposed OQ Clos-UDN outperforms previous proposals and maintains high throughput and latency performance.