A new calibration setup for lock-in amplifiers in the low frequency range and its validation in a bilateral comparison

Cultrera, Alessandro; Corminboeuf, D.; D'Elia, Vincenzo; Tran, Ngoc Thanh Mai; Callegaro, Luca; Ortolano, Massimo

doi:10.1088/1681-7575/abdae0

Cited by 7 publications

(4 citation statements)

References 20 publications

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“…宽与信噪比的标定, 通常离不开经过计量校准的信号源, 在前述校准规范中, 也都是采用从电压基准间接传递过来的信号源, 为了进一步提高测试信号的准确性, 近些年在交流信号基准方面也有一些进展. 河北大学王彪与中国计量院张江涛等 [43] 利用四端互感将锁相放大器溯源到交流电压标准和交流电阻标准上, 进行锁相放大器正交分量的溯源, 以四端互感和三支路电抗分流器为基础, 在量程 5 mV, 20-200 kHz频率之间对锁相放大器进行校准, 不确定度评定结果在4/1000以内. 意大利国家计量研究所Cultrera研究组 [44] 开展了锁相放大器在低频范围内的校准, 通过欧洲跨实验室锁相标定比对, 显示亚千赫兹频率与微伏幅度下, 锁相放大器的相对不确定度在1/10000量级.…”

Section: 在锁相放大器的计量过程中幅度、相位、带unclassified

Research progress of lock-in amplifiers

Guo,

Li,

et al. 2023

Acta Phys. Sin.

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The lock-in amplifier can perform high-precision measurement in both time and amplitude dimensions, so that it becomes a key component of instrumental system for precision measurement and control. This article overviews the concept, technology, and application of phase-locked amplifiers as a guide. It first explains the development and evolution of phase-locked amplifiers of analog, digital, and virtual phase-locked amplifiers, demonstrating their relationship and differences. Then, it classifies phase-locked amplifiers from a mathematical perspective based on the order and type of phase-locked loops. Subsequently, the testing process and metrological calibration progress of the main performance of phase-locked amplifiers, such as amplitude, frequency, and phase noise, are introduced. The conversion relationship between key indicators such as phase noise, time-domain jitter, Allen variance, and the coupling relationship with amplitude noise are discussed. Finally, the application forms and effects of phase-locked amplifiers in the fields of spectral enhancement, impedance analysis, magnetic measurement, microscopic imaging, and space exploration are listed. Through some new applications, the prospects of their transition from scientific instruments to industrial and even civilian products through intelligent computing, precise IoT, and other means are briefly given.

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Section: 在锁相放大器的计量过程中幅度、相位、带unclassified

Research progress of lock-in amplifiers

Guo,

Li,

et al. 2023

Acta Phys. Sin.

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“…Here, µ FE was determined using the maximum transconductance method, and V TH was defined as the gate-to-source voltage (V GS ) that induces a drain current (I D ) of 1 nA at V DS = 0.1 V [17]. Figure 4 shows the C-V characteristics measured between the gate and source/drain electrodes of the fabricated IGZO TFTs at a low frequency of 103 Hz, where the value of the measurement frequency was chosen to minimize the interference from the power-line harmonics, as per the results of previous reports for a lock-in amplifier [18]. Adding both sources of charge,…”

Section: Resultsmentioning

confidence: 99%

Comparative Study on the Separate Extraction of Interface and Bulk Trap Densities in Indium Gallium Zinc Oxide Thin-Film Transistors Using Capacitance–Voltage and Current–Voltage Characteristics

et al. 2021

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The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (C–V) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the C–V curve, the energy distribution of the interface trap density was extracted using the low-frequency C–V characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs.

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“…Chen et al [ 4 ] proposed a method based on integral average digital lock-in amplifier (IADLIA) to reduce the distortion and output fluctuation of detection results of digital lock-in amplifier (DLIA). Cultrera et al [ 5 ] proposed a setup to get calibration of lock-in amplifiers, discussed the calibration of lock-in amplifier in low frequency range. Alves et al [ 6 ] proposed a method to obtain an enhanced frequency resolution two-phase lock-in amplifier with two channels in a microcontroller using minimum external circuitry, which can increase the frequency resolution by 1000 times.…”

Section: Introductionmentioning

confidence: 99%