2022
DOI: 10.3390/ma15196690
|View full text |Cite
|
Sign up to set email alerts
|

A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching

Abstract: A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower Ron,sp, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% l… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2023
2023
2024
2024

Publication Types

Select...
6

Relationship

0
6

Authors

Journals

citations
Cited by 6 publications
(2 citation statements)
references
References 14 publications
0
2
0
Order By: Relevance
“…Zhenfeng Peng [11] developed an HJD-MOSFET based on conventional 4H-SiC CON-DTMOSFET, achieving an 𝑅 𝑜𝑛,𝑠𝑝 of 2.6 𝑚Ω • 𝑐𝑚 2 in simulation. Zhu, S et al used dodecagonal cell topology to decrease planar MOSFET on-resistance by 2.2x [12]. H. Yu et al introduced an SP-structure, forming a JBS-MOSFET for better SC quality [13], reaching an onresistance of 2.0 𝑚𝛺 • 𝑐𝑚 2 .…”
Section: Sic Based Mosfetsmentioning
confidence: 99%
“…Zhenfeng Peng [11] developed an HJD-MOSFET based on conventional 4H-SiC CON-DTMOSFET, achieving an 𝑅 𝑜𝑛,𝑠𝑝 of 2.6 𝑚Ω • 𝑐𝑚 2 in simulation. Zhu, S et al used dodecagonal cell topology to decrease planar MOSFET on-resistance by 2.2x [12]. H. Yu et al introduced an SP-structure, forming a JBS-MOSFET for better SC quality [13], reaching an onresistance of 2.0 𝑚𝛺 • 𝑐𝑚 2 .…”
Section: Sic Based Mosfetsmentioning
confidence: 99%
“…These techniques include self-aligned channel [2,3], self-aligned source contact [4], specific doping on JFET region [5], and current spreading layer [6]. On the design front, cell topology and pitch reduction play vital roles in further improving the performance of VDMOSFETs [7][8][9][10][11][12][13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%