A new channel percolation model for V/sub T/ shift in discrete-trap memories

Ielmini, Daniele; Compagnoni, Christian Monzio; Spinelli, A.S.; Lacaita, A.L.; Gerardi, C.

doi:10.1109/relphy.2004.1315382

Cited by 13 publications

(5 citation statements)

References 19 publications

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“…It is believed that the additional instability is due a discrete random trapped charge effect, similar to what has been recently observed for discrete-trap memories [4]. The trapped charge can occur at random locations across the gate and can affect the drain current de-pending on the local current density.…”

supporting

confidence: 53%

Random charge effects for PMOS NBTI in ultra-small gate area devices

Agostinelli

Pae

Yang

et al.

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.

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PURPOSE PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated [I J, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.PMOS NBTI transistor degradation is an important reliability mechanism and has been shown to be one of the major limiters for product lifetime [2,3].PMOS N3TI effects originate from the formation of fixed oxide charge and the creation of interface states. These effects manifest themselves as shifts in threshold voltage and transconductance, For large gate area devices, these shifts can cause failure of digital circuits to meet timing windows or can create undesirable mismatch in analog circuits.Recent observations on PMOS devices with small gate areas show that the degradation of both drain current and threshold voltage appear to be subject to random fluctuations.These fluctuations increase a5 a function of stress time and are affected by the current density. It is believed that the additional instability is due a discrete random trapped charge effect, similar to what has been recently observed for discrete-trap memories [4]. The trapped charge can occur at random locations across the gate and can affect the drain current de-pending on the local current density. This paper examines the effects of PMOS NBTI-induced random fluctuations on device degradation. It clearly demonstrates that this geometric effect is due to the statistical nature of random trapped charge in the oxide and the effect of this charge on the percolation path through the channel of a small gate area device. MODELINGThe statistical nature of the random charge effect can be modeled in a similar fashion as has been done for random dopants. Charges placed at discrete points in the channel region can constrict the current flow in a small gate area devices by locally modifylng the threshold voltage. As illustrated in Figure 1, if random charges are placed at discrete points along a conducting path from source to drain, the current flow will be forced to areas of lower threshold voltage and could possibly be shut off entirely. CHANKEL FIGURE 1: ILLUSTRATION OF CURRENT FLOW FROM SOURCE TO DRAW IN A SMALL GATE AREA DEVICE. OPEN CIRCLE REPRESENT FILLED TRAPS THAT ALTER THE CURRENT FLOW FROM SOURCE TO DRAIN. Keyes [5] derived a relationship expressing the fluctuation in the threshold voltage as a function of channel doping and gate area. In this derivation, the probability of a conducting path from source to drain is determined by the local probability of a given area in the channel having a number of impurities less than a critical threshold, m,. This probability can be...

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supporting

confidence: 53%

Random charge effects for PMOS NBTI in ultra-small gate area devices

Agostinelli

Pae

Yang

et al.

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.

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“…These fluctuations probably originate from the random variations in the number and spatial distribution of the charges that were formed in the oxide and at the interface. Therefore, the I d of the device will, in turn, randomly fluctuate according to the current percolation theory [13], [14]. Because the single-point method used in Fig.…”

Section: Device Structure and Experimentsmentioning

confidence: 99%

“…The efficient suppression of NBTI fluctuation with this online I g method can be simply explained by the following facts. Because the measured I d is directly influenced by the trapped charges in its local percolation path, the I d will fluctuate if the charges are randomly trapped [13], [14]. However, due to the global behavior of changing the oxide electric field, the measured I g will not fluctuate, which can better characterize the NBTI behavior of short-channel SNWFETs.…”

Section: Characterization Techniques For Suppressing the Nbti Flucmentioning

confidence: 99%

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

Wang

Huang

et al. 2008

IEEE Electron Device Lett.

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In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In longchannel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO 2 interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.Index Terms-Fluctuation, gate current, negative bias temperature instability (NBTI), reliability, silicon nanowire field-effect transistor (SNWFET).

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“…In contrast with FG memories, where the presence of a high doped polysilicon floating gate assures the channel potential uniformity, in NCMs each electron stored in a nanodot influences only the electrostatic potential of the neighboring channel region. These results in a non-uniform channel potential: when enhancing the gate voltage, the substrate inversion occurs first in those regions far from negative charged nanocrystals [27]. The conduction through the channel of the cell is then not uniform, and takes place only in a small part of the gate area.…”

Section: Subthreshold Slopementioning

confidence: 99%

Radiation-Induced Modifications of the Electrical Characteristics of Nanocrystal Memory Cells and Arrays

Gasperin

Cester

Wrachien³

et al. 2006

IEEE Trans. Nucl. Sci.

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Proton irradiation on Nanocrystals Memories\ud produces peculiar radiation effects on the electrical\ud characteristics of these devices, owing to their thin tunnel oxide\ud and to the presence of nanocrystals replacing the Flash memory\ud conventional floating gate. In this work we show that the data\ud retention capability is compromised only after high fluences and\ud that irradiated devices do not show accelerated degradation\ud during subsequent electrical stresses. The presence of\ud nanocrystals instead of a floating gate reduces also the quantity\ud of charge lost during irradiation, indicating these devices as\ud possible candidates for space and avionic environment

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A new channel percolation model for V/sub T/ shift in discrete-trap memories

Cited by 13 publications

References 19 publications

Random charge effects for PMOS NBTI in ultra-small gate area devices

Random charge effects for PMOS NBTI in ultra-small gate area devices

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

Radiation-Induced Modifications of the Electrical Characteristics of Nanocrystal Memory Cells and Arrays

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