A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Abstract

The total power in a device is composed of three basic components, having dynamic power due to switching activity, static power while the device in sleep mode and short circuit power while a short amount of current flows from power supply rail (VDD) to ground terminal (GND). The dynamic power component in a CMOS circuit is dominating at lower technology nodes. With scaling, having lesser than 65nm regime the leakage power increases than dynamic power that becomes challenging for the VLSI design engineers. This paper describes a new circuit level leakage power reduction technique called as Input Leakage Controlled Stack Transistor-ILCST for CMOS circuits at circuit level that is been used in 4-bit flash Analog to Digital Converter applicable for deep brain neurostimulator. Analog to Digital Converters (ADC) are crucial for transforming analogue signals from the real world into digital data in the form of 0 and 1. Flash is the most popular ADC owing to its fast speed nature. In this study, a 4-bit flash ADC with a, sample and hold (S/H), comparators and a priority encoder are designed and simulated. To perform sampling process, the sample and hold circuit is utilized. An encoder is a necessary component of a Flash ADC. It converts the comparator output-generated thermometer code (TC) into binary code (BC). The speed, area, and power must all be taken into account while designing the flash analogue to digital converter. Work is implemented using 45nm technology node and carried the simulations in Cadence Virtuoso tool. The static power is reduced significantly using the proposed technique.