A new code generation algorithm for 2-offset producer order queue computation model

Canedo, Arquimedes; Abdallah, Abderazek Ben; Sowa, Masahiro

doi:10.1016/j.cl.2007.06.003

Cited by 14 publications

(20 citation statements)

References 11 publications

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“…Together with the 2-offset P-Code QCM we developed the compiler infrastructure and code generation algorithms [4]. Our queue compiler uses GCC 4.0.2 front-end.…”

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

“…Figure 3 shows the structure of the queue compiler. We conducted experiments to measure the distribution of P-Code instructions required by some scientific test programs and the 2-offset P-Code QCM [4]. We found that the instructions that require the two operands to be dequeued from a different position than QH (2-offset instructions) appear rarely in programs.…”

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

“…Thus, PQP instruction set format requires the encoding of the offset references making it longer than the instruction set for a traditional queue machine. We found in [4], that for a set of scientific programs the instructions that require two offsets are almost nonexistent. Below 10% of the instructions require only one offset reference, and above 90% of remaining instructions require no offsets to be specified.…”

Section: Introductionmentioning

confidence: 99%

“…Figure 5 shows the two stages for the proposed code generation algorithm represented by the numbered circles. The elements inside the dashed area are the modified modules with respect of the original queue compiler [4] shown in Figure 3. …”

Section: Code Generation Algorithmmentioning

confidence: 99%

“…In our early work [4], we have proposed a 2-offset P-Code QCM to allow programs to be generated directly from their directed acyclic graphs (DAGs). 2-offset P-Code QCM, strictly follows enqueueing rule but has flexibility in the dequeueing rule of operands.…”

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

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An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Canedo

Abdallah

Sowa

Embedded and Ubiquitous Computing

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Abstract. Embedded systems very often demand small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a dual instruction set. This approach reduces code size at the cost of performance degradation due to the greater number of reduced width instructions required to execute the same task. We propose a novel alternative for reducing code size by using a single reduced instruction set queue machine. We present a efficient code generation algorithm to insert additional instructions to be able to execute programs in the reduced instruction set. Our experiments show that the insertion of additional instructions is minimal and we demonstrate improved code size reduction of 16% over MIPS16, 26% over Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler without any optimization is able to extract about the same parallelism than fully optimized RISC code.

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“…Together with the 2-offset P-Code QCM we developed the compiler infrastructure and code generation algorithms [4]. Our queue compiler uses GCC 4.0.2 front-end.…”

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Code Generation Algorithmmentioning

confidence: 99%

Section: -Offset P-code Queue Computation Modelmentioning

confidence: 99%

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An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Canedo

Abdallah

Sowa

Embedded and Ubiquitous Computing

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Parallelizing Compiler for Single and Multicore Computing

Abdallah¹

2017

Advanced Multicore Systems-on-Chip

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Dual-execution mode processor architecture

2007

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In this research work, we propose a novel embedded dual-execution mode 32-bit processor architecture (QSP32), which supports queue and stack programming models. The QSP32 core is based on a high performance produced order parallel queue architecture and is targeted for applications constrained in terms of area, memory, and power requirements. The design focuses on the ability to execute queue programs and also to support stack programs without a considerable increase in hardware to the base queue architecture. A prototype implementation of the processor is produced by synthesizing the high level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. From the design and evaluation results, the QSP32 core efficiently executes both queue and stack based programs and achieves on average about 65 MHz speed. In addition, when compared to the base single-mode architecture (PQP), the QSP32 core requires only about 2.41% additional hardware. Moreover, the prototype fits on a single FPGA device, thereby eliminating the need to perform multi-chip partitioning which results in a loss of resource efficiency.

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A new code generation algorithm for 2-offset producer order queue computation model

Cited by 14 publications

References 11 publications

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Parallelizing Compiler for Single and Multicore Computing

Dual-execution mode processor architecture

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