2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2016
DOI: 10.1109/ispsd.2016.7520879
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A new concept of a high-current power module allowing paralleling of many SiC devices assembled exploiting conventional packaging technologies

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Cited by 24 publications
(7 citation statements)
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“…As a conclusion, it can be stated that this solution increases the total parasitic impedance of the power module, since the area dedicated to the power signals is reduced [277]. The twisted configuration provides a reduction of the gate loop stray inductance L gate because the wire coupling effect M ef f ect is greater, as it can be seen from ( 5).…”
Section: T1mentioning
confidence: 84%
“…As a conclusion, it can be stated that this solution increases the total parasitic impedance of the power module, since the area dedicated to the power signals is reduced [277]. The twisted configuration provides a reduction of the gate loop stray inductance L gate because the wire coupling effect M ef f ect is greater, as it can be seen from ( 5).…”
Section: T1mentioning
confidence: 84%
“…SiC metal oxide semiconductor field effect transistor (SiC-MOSFET) switches, in addition to having characteristics of lower conduction and switching loss compared to Si insulated gate bipolar transistors (IGBTs), have high switching capability that make these switches appropriate for high speeds and high frequency motor drive systems [214,215]. The recent SiC MOSFET devices are rated for 1200 V and 1700 V [216]. The technological development assessment in these areas suggests that in 15 to 30 years there is a possibility to achieve efficiency and SP in the range of 98%-99%, 16.5-25 kW/kg respectively in a non-cryogenic system [105].…”
Section: Pmsmmentioning
confidence: 99%
“…Further, to overcome the current limitation of PCB, dies are soldered on the lower layer by using "DBC/Solder/DBC" stacked structure with power loop inductance 6nH [17] and 1.8nH [18]. Similarly, "DBC/Solder/DBC/Solder/DBC" stacked structure are used with power loop inductance 11nH [19]. Dies can also be soldered on the up layer by using Cu/Si 3 N 4 /Cu/Si 3 N 4 /Cu AMB structure with power loop inductance 5nH [20][21] and 1.15nH [22].…”
Section: Introductionmentioning
confidence: 99%