A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

Gaffour, Khadidja; Benhaoua, Mohammed Kamel; Benyamina, A. H.; Zahaf, H. E.

doi:10.1080/1206212x.2019.1679529

Cited by 5 publications

(4 citation statements)

References 19 publications

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“…For simulation, the Newxim simulator [47] (a deeply revised version of the well-known Noxim simulator [48,49]) is used, which supports circulant topologies and the ability to easily implement any custom routing algorithms, as well as many automation tools that greatly speed up and facilitate the process of modeling and processing results.…”

Section: Evaluation and Discussionmentioning

confidence: 99%

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

Sukhov,

Romanov,

Selin

2024

Symmetry

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In this work, the circulant topology as an alternative to 2D mesh in networks-on-chip is considered. A virtual coordinate system for numbering nodes in the circulant topology is proposed, and the principle of greedy promotion is formulated. The rules for constructing the shortest routes between the two nodes based on coordinates are formulated. A technique for calculating optimal network configurations is described. Dense states of the network when all neighborhoods of the central node are filled with nodes and the network has the smallest diameter are defined. It is shown that with an equal number of nodes, the diameter of the circulant is two times smaller than the diameter of the 2D mesh. This is due to the large number of symmetries for the circulant, which leave the set of nodes unchanged. A comparison of communication stability in both topologies in the conditions of failure of network nodes is made, the network behavior under load and failures is modeled, and the advantages of the circulant topology are presented.

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Section: Evaluation and Discussionmentioning

confidence: 99%

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

Sukhov,

Romanov,

Selin

2024

Symmetry

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“…In situations where there is a high volume of communication, central routers may experience contention and congestion, leading to elevated levels of latency and power consumption. To tackle these challenges, the concept of a Three-Dimensional Network-on-Chip has been put forth as a potential remedy to enhance the overall performance in terms of throughput, latency, and energy efficiency [59]. This paper [60] presented a novel NoC SerDes transceiver architecture specifically developed for facilitating long-distance interconnectivity within MPSoCs.…”

Section: Rts Noc-based Mpsoc: Taxonomymentioning

confidence: 99%

“…In terms of context direction, the analyses of the adaptability and flexibility of routing algorithms in the context of heterogeneous multicore architectures and the cooperation of specialised accelerators [60], [70] and considering the effects of privacy and accuracy concerns on the design and application of routing algorithms, especially in NoCs for safety-critical structures are vital context directions [63]. Moreover, characteristics directions can be examine the trade-offs between performance indicators, including latency, throughput, and energy usage, when designing and refining routing algorithms for NoCs [59], [64] and investigating the effect of application-specific criteria on the design and optimisation of routing algorithms [51]. Furthermore, the methodology directions can be investigated based on exploring an opportunity for reinforcement learning algorithms, such as Q-learning or deep Q-networks, in improving the decision-making process of routing algorithms for NoCs and investigating the implementation of computational optimisation techniques, such as linear programming or evolutionary techniques, to fine-tune routing algorithms and accomplish global optimisation [66].…”

Section: Congestion Controlmentioning

confidence: 99%

181Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip forIOT:A Systematic Review

2024

Iraqi Journal for Computer Science and Mathematics

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Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data from credible resources, including IEEE Xplore ®, ScienceDirect, Association for Computing Machinery and Web of Science. Out of the 906 research papers reviewed, only 51 were considered relevant to the investigation on NoC RTs. The study addresses issues related to NoC routing and suggests new approaches for in-package data negotiating. In addition, it gives an overview of the recent research on routing strategies and numerous algorithms that can be used for NoC-based MPSoCs. The literature analysis addresses current obstacles and delineates potential future avenues, recommendations, and challenges analyzing techniques to assess performance utilizing metrics within the TCCM framework.

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“…They propose SBTR and e-SBTR router architectures. Gaffour et al [44] propose a Minimal-Congestion-aware-Routing-Algorithm that utilizes local congestion information for structuring global routing strategy in 2D/3D NoC. It computes free buffer status and stores it in the flag as three levels: highly congested, congested, and non-congested.…”

Section: ) Congestion Propagation Network -Using Dedicated Wirementioning

confidence: 99%

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

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Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

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A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

Cited by 5 publications

References 19 publications

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

181Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip forIOT:A Systematic Review

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

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