A new coplanar design of a 4‐bit ripple carry adder based on quantum‐dot cellular automata technology

Seyedi, Saeid; Pourghebleh, Behrouz; Navimipour, Nima Jafari

doi:10.1049/cds2.12083

Cited by 23 publications

(12 citation statements)

References 42 publications

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“…The second implementation of the adder uses 209 cells with an area of 0.25 µm 2 with the same latency. Saeid Seyedi et al [22] have designed a nano-scale RCA in order to minimize the cell number and delay thereby improving the complexity of the circuit. The proposed co-planar design uses 89 cells in 0.12 µm 2 but giving a delay of 3.75 clock cycles which results in an increase in the quantum cost.…”

Section: Qca Basic Conceptsmentioning

confidence: 99%

A Novel Cost-efficient Parallel Binary Adder without Crossover in QCA with Energy Dissipation Analysis

Chugh

Singh

2023

Preprint

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Quantum dot cellular automata(QCA) is a computational paradigm which uses tiny semiconductor crystals as the basic units of information in computer circuits that can be used to process information similar to transistors. This work introduces a novel half-adder design in single-layer using 90◦ cells in a single clock zone. Moreover, a full adder circuit using 37 cells in one layer with 0.5 latency is proposed which further forms the basis of a nano-scale parallel binary adder(RCA) design in QCADesigner v2.0.3. The proposed 4-bit design uses 174 cells without the use of any cross-wiring with a latency of only 1 clock. The detailed energy dissipation study of the circuits is also investigated for different tunneling energies using the QCAPro tool. The comparison results of the adder circuits in respect of quantum cost, latency, cell count and total average energy dissipation show significant improvement as compared to the latest QCA-based adder designs.

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Section: Qca Basic Conceptsmentioning

confidence: 99%

A Novel Cost-efficient Parallel Binary Adder without Crossover in QCA with Energy Dissipation Analysis

Chugh

Singh

2023

Preprint

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“…Furthermore, to measure the proposed full-adder complexity, we used the QCA cost function. The cost function is expressed as follows 39,40 :…”

Section: Comparisonsmentioning

confidence: 99%

“…Also, k, l, p are the weights for majority gate, crossover, and delay, respectively. 39,40 In this part, different values (between 1 and 4) are considered for these weights to compare them better. As shown in Table 5, the proposed full-adder has enhanced performance than its counterparts in terms of cost.…”

Section: Comparisonsmentioning

confidence: 99%

Designing a multi‐layer full‐adder using a new three‐input majority gate based on quantum computing

Seyedi

Navimipour

2021

Concurrency and Computation

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Recently, quantum dot-cellular automata (QCA) has fascinated much attention because of its potential less area consumption, low power usage, less intricacy, and low delay. The full-adder circuit is used in this technology for several procedures, like multiplication, subtraction, and division in the arithmetic logic unit. For this reason, the full-adder is generally investigated as a central unit in the development of QCA technology. The present investigation demonstrates a new efficient QCA-based full-adder layout utilizing the TIEO gate and new 3-input majority gate. In this design, the inputs get inside one side, and the outputs are derived from another circuit side. Other cells do not embrace the output and input signals, and they may simply be available, helping produce a more impressive circuit layout. Concretely speaking, in this design, the 0.02 μm 2 region and the latency of the 0.5 clock cycle have been implemented using only 18 cells. Utilizing the QCADesigner tool, the suggested design in the current investigation has been functionally approved. The simulation outcomes show that this layout conducts properly and works faster than the oldest designs.

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“…Furthermore, in order to apply the suggested fault-tolerant 1:2 demultiplexer complexity, we practiced its QCA cost function. The cost function can be calculated as follows [38,39]:…”

Section: Cell Defect Analysismentioning

confidence: 99%

Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

2021

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Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

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A new coplanar design of a 4‐bit ripple carry adder based on quantum‐dot cellular automata technology

Cited by 23 publications

References 42 publications

A Novel Cost-efficient Parallel Binary Adder without Crossover in QCA with Energy Dissipation Analysis

A Novel Cost-efficient Parallel Binary Adder without Crossover in QCA with Energy Dissipation Analysis

Designing a multi‐layer full‐adder using a new three‐input majority gate based on quantum computing

Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

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