2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops 2014
DOI: 10.1109/ipdpsw.2014.18
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A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware

Abstract: Abstract-While custom (and reconfigurable) computing can provide orders-of-magnitude improvements in energy efficiency and performance for many numeric, data-parallel applications, performance on non-numeric, sequential code is often worse than what is achievable using conventional superscalar processors. This work attempts to address the problem of improving sequential performance in custom hardware by (a) switching from a statically scheduled to a dynamically scheduled (dataflow) execution model, and (b) dev… Show more

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Cited by 7 publications
(9 citation statements)
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“…These properties along with its simple construction from a language's abstract syntax tree made the CFG in SSA form the predominant IR for imperative language compilers [44], such as LLVM [22] and GCC [10]. However, the CFG has also been criticized as an IR for optimizing compilers [15,19,20,24,[48][49][50]:…”
Section: Control (Data) Flow Graphmentioning
confidence: 99%
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“…These properties along with its simple construction from a language's abstract syntax tree made the CFG in SSA form the predominant IR for imperative language compilers [44], such as LLVM [22] and GCC [10]. However, the CFG has also been criticized as an IR for optimizing compilers [15,19,20,24,[48][49][50]:…”
Section: Control (Data) Flow Graphmentioning
confidence: 99%
“…The restoration of a program with an eager evaluation semantics complicates destruction immensely, and requires a detour over the PDG to arrive at a unique CFG [24]. Zaidi et al [49,50] adapted the VSDG to spatial hardware and sidestepped this problem by introducing a predication-based eager/dataflow semantics. The idea is to effectively enforce correct evaluation of operations with side-effects by using predication.…”
Section: Value (State) Dependence Graphmentioning
confidence: 99%
“…Incorporation of the conventional processor and spatial architecture can effectively balance the sequential and parallel applications, offering a more flexible programming model, and provides more energy efficiency than pure conventional processors. But it also suffers the advantages of the energy efficiency of the spatial part for that the conventional processor cannot be shut downed while the workloads are all in the DySER blocks [4]. In [9], they evaluated a 64-functional-unit DySER block with dual-issue out-of-order processor on PARSEC, SPEC and Parboil benchmarks, obtained a 2.1x speedup and 40% energy reduction.…”
Section: Implementations Of Spatial Computing Architecture 211 Dysermentioning
confidence: 99%
“…Without PC, the instructions in Wavescalar architecture are dynamically scheduled by dataflow instead of control flow. But unlike other static-dataflow architecture, Wavescalar's dynamic dataflow is similar to the out-of-order superscalar processor, but currently, it not supports the control speculation [4].…”
Section: Wavescalarmentioning
confidence: 99%
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