A new degree of freedom for memory allocation in clusters

Abstract

Fröning, H.; Duato Marín, JF. (2012). A new degree of freedom for memory allocation in clusters. Cluster Computing. 15(2):101-123. doi:10.1007/s10586-010-0150-7.Noname manuscript No. (will be inserted by the editor) A New Degree of Freedom for Memory Allocation in ClustersHéctor Montaner · Federico Silla · Holger Fröning · José DuatoReceived: date / Accepted: date Abstract Improvements in parallel computing hardware usually involve increments in the number of available resources for a given application such as the number of computing cores and the amount of memory. In the case of shared-memory computers, the increase in computing resources and available memory is usually constrained by the coherency protocol, whose overhead rises with system size, limiting the scalability of the final system. In this paper we propose an efficient and cost-effective way to increase the memory available for a given application by leveraging free memory in other computers in the cluster.Our proposal is based on the observation that many applications benefit from having more memory resources but do not require more computing cores, thus reducing the requirements for cache coherency and allowing a simpler implementation and better scalability.Simulation results show that, when additional mechanisms intended to hide remote memory latency are used, execution time of applications that use our proposal is similar to the time required to execute them in a computer populated with enough local memory, thus validating the feasibility of our proposal. We are currently building a prototype that implements our ideas. The first results from real executions in this prototype demonstrate not only that our proposal works but also that it can efficiently execute applications that make use of remote memory resources.

A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing

“…Our architecture shares concepts with the approach presented in [10] for disaggregated memory. To maintain a simple hardware controller design, requiring only a few configuration registers, the authors prefer to integrate all the remote memory forwarding information in the physical address and exploit the OS page translation infrastructure for accessing remote memory.…”

A software-defined architecture and prototype for disaggregated memory rack scale systems

“…Our work evaluates a similar approach on real hardware showcasing a prototype based on a commercial SoC, aiming at appreciating the production potential of the approach to benchmarks and representative applications. To that end, we aim to extend our approach to incorporate targeted OS-level innovation to further improve application-perceived memory performance and expand to further applications to directly compare our findings to [22].…”