A New Design of Clock Synchronization Algorithm

Liu, Jingmeng; Li, Xuerong; Liu, Min; Cui, Xikui; Xu, Dong

doi:10.1155/2014/958686

Cited by 6 publications

(6 citation statements)

References 15 publications

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“…Consider the K c parameter in the clock model. The details for the calculation of this value are presented in (19) to (21). In formula (21), K c belongs only to the phase lock loop frequency f PLL .…”

Section: B Resultsmentioning

confidence: 99%

“…Alternatively, a fine update is performed when a small time offset is reached. The details of this module can be found in [19].…”

Section: Proposed Adaptive Clock Synchronization Methodsmentioning

confidence: 99%

“…The K P and K I parameters belong to the system in an off-line way. Using the integral square error method [18], a deadbeat PI controller (the optimal PI servo) is designed to minimize the integral square time offset [19]- [23]. The K P and K I parameters are fixed and belong to the time synchronized interval and clock model parameters, respectively.…”

Section: Related Workmentioning

confidence: 99%

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An Adaptive Fuzzy-PI Clock Servo Based on IEEE 1588 for Improving Time Synchronization Over Ethernet Networks

Nguyen

Jeon

2020

IEEE Access

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A network-based control system includes many connected devices, and time synchronization plays an important role in the unified operation of those systems. A clock servo needs a guarantee time offset and a clock rate to minimize the time difference between devices. This paper proposes an adaptive clock servo to improve time synchronization. This proposed algorithm uses a fuzzy-based proportional-integral clock servo (fuzzy-PI) based on IEEE 1588 to reduce the frequency of clock compensation. This method adapts the bandwidth and enhances noise reduction, improving both the time offset and rate difference between the slave and master. The node time can synchronize with the master time after just one cycle of synchronization. Experiments validated the effectiveness of the algorithm and demonstrated that the slave can track the master with the mean and standard deviation of the time offset are 0.432ns and 4.402ns. A cycle time of one second is used to ensure a low-bandwidth network. With these results, the number of nodes over a real-time network can be increased.

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Section: B Resultsmentioning

confidence: 99%

“…Alternatively, a fine update is performed when a small time offset is reached. The details of this module can be found in [19].…”

Section: Proposed Adaptive Clock Synchronization Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

An Adaptive Fuzzy-PI Clock Servo Based on IEEE 1588 for Improving Time Synchronization Over Ethernet Networks

Nguyen

Jeon

2020

IEEE Access

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“…A clock servo is a control system that uses frequency compensation to periodically correct the time offset [25]. There are many studies on clock servo [26][27][28][29][30][31][32][33][34], but few provide a detailed evaluation of synchronization performance under QIDA.…”

Section: Introductionmentioning

confidence: 99%

A Fuzzy-PI Clock Servo with Window Filter for Compensating Queue-Induced Delay Asymmetry in IEEE 1588 Networks

Zhang,

Li,

Wang

et al. 2024

Sensors

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Clock synchronization is one of the popular research topics in Distributed Measurement and Control Systems (DMCSs). In most industrial fields, such as Smart Grid and Flight Test, the highest requirement for synchronization accuracy is 1 μs. IEEE 1588 Precision Time Protocol-2008 (PTPv2) can theoretically achieve sub-microsecond accuracy, but it relies on the assumption that the forward and backward delays of PTP packets are symmetrical. In practice, PTP packets will experience random queue delays in switches, making the above assumption challenging to satisfy and causing poor synchronization accuracy. Although using switches supporting the Transparent Clock (TC) can improve synchronization accuracy, these dedicated switches are generally expensive. This paper designs a PTP clock servo for compensating Queue-Induced Delay Asymmetry (QIDA), which can be implemented based on ordinary switches. Its main algorithm comprises a minimum window filter with drift compensation and a fuzzy proportional–integral (PI) controller. We construct a low-cost hardware platform (the cost of each node is within USD 10) to test the performance of the clock servo. In a 100 Mbps network with background (BG) traffic of less than 70 Mbps, the maximum absolute time error (max |TE|) does not exceed 0.35 μs, and the convergence time is about half a minute. The accuracy is improved hundreds of times compared with other existing clock servos.

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“…As the transmission bus for instructions and data, Ethernet is used to connect various nodes in distributed systems [5]. Many time synchronization algorithms in network-based communication have been proposed, and their time synchronization accuracy and implementation complexity are different [6,7]. There are two main time synchronization algorithms that have formed a standard and have been applied in practice: Network Time Protocol (NTP) and Precision Time Protocol (PTP).…”

Section: Introductionmentioning

confidence: 99%

Design considerations for hardware implementation of nanoseconds time synchronization low-cost system based on precise time protocol

2022

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Precise time synchronization is the key for coordinating every node of the distributed system to complete tasks. The widespread use of Field Programmable Gate Array (FPGA) in distributed nodes has a positive effect on improving time synchronization accuracy. Although the use of FPGA could significantly improve time synchronization accuracy, there is not a universal design guideline. This work has analyzed and summarized three factors that should be considered when building a low-cost clock synchronization system using FPGA: where the timestamp should be generated, the calculation and correction of time offset, and how to handle Precise Time Protocol (PTP) messages. Based on these design considerations, the time synchronization system intellectual property (IP) core was constructed. The synchronization accuracy experiments have been performed on Zynq system-on-chip (SoC) evaluation boards of different architectures. The experimental results demonstrated that the time synchronization system constructed in this article could achieve nanoseconds accuracy.

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A New Design of Clock Synchronization Algorithm

Cited by 6 publications

References 15 publications

An Adaptive Fuzzy-PI Clock Servo Based on IEEE 1588 for Improving Time Synchronization Over Ethernet Networks

An Adaptive Fuzzy-PI Clock Servo Based on IEEE 1588 for Improving Time Synchronization Over Ethernet Networks

A Fuzzy-PI Clock Servo with Window Filter for Compensating Queue-Induced Delay Asymmetry in IEEE 1588 Networks

Design considerations for hardware implementation of nanoseconds time synchronization low-cost system based on precise time protocol

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