A new design of double edge triggered flip-flops

Pedram, Massoud; Wu, Qing; Wu, Xiugang

doi:10.1109/aspdac.1998.669513

Cited by 58 publications

(19 citation statements)

References 9 publications

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“…It varies with different data rates and circuit topologies. Hence to obtain a fair idea of power dissipation for a circuit topology, different data patterns should be applied with different activity rates [16]- [18]. So in simulations, following six different data sequences have been adopted to compare the power consumption of flip-flop structures discussed in this paper: i) 1111111111111111 ii) 0000000000000000 iii) 1111010110010000 iv) 1100110011001100 v) 1010101010101010 vi) 0100000000000000 Power increases on optimizing a circuit for delay and vice versa.…”

Section: Simulation Conditionsmentioning

confidence: 99%

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Power Efficient Dual Edge-Triggered Storage Design

Khan¹,

Hasan²

2017

IJET

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Abstract-In this work, four conventional most commonly referred master slave dual-edge-triggered storage designs are analyzed. The power efficient master slave dual-edge-triggered storage design is also proposed. A detailed comparison of the existing and proposed designs is presented in this work. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that the proposed design has the least power consumption for all data patterns, all supply voltages and all clock frequencies among all the discussed designs and has up to 97.41% lesser power consumption than existing designs. The proposed design has lesser PDP than all existing designs and has up to 97.63% improvement in PDP. The design has improvements in terms of power dissipation and PDP with reduced silicon area. The proposed design is suitable for low power applications of all data patterns and is also suitable for low area applications.Keyword -Edge triggered, Pass Transistor, Parasitic capacitance, propagation delay, clocked transistor I. INTRODUCTION The rapid scaling of silicon technology has enabled designers to integrate millions and even billions of transistors into a single chip. However, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density. So, the need for power-efficient design techniques has grown considerably [1]- [3]. The latest advances in mobile battery-powered devices have set new goals in digital VLSI design. These devices require high speed and low power consumption. So, the low power design is must for the applications operated by batteries such as pocket calculators, wrist watches, mobile phones, laptops etc. It is important to prolong the battery life as much as possible [4]- [8]. High power dissipation of a SoC will not only increase its system costs but also affect the product lifetime and reliability. Minimizing power dissipation increases lifetime and reliability of the circuit [9].Voltage scaling is the most effective way to decrease power consumption, since power is proportional to the square of the supply voltage. However, voltage scaling is associated with threshold voltage scaling which can cause the leakage power to increase exponentially [10]. By using dual-edge triggered flip-flops (DETFFs), the clock frequency can be significantly reduced-ideally, cut in half-while preserving the rate of data processing [11]. In many digital VLSI designs, the clock system that includes clock distribution network and flip-flops is one of the highest power consuming components and accounts for 30% to 60% of the total system power, out of which 90% is consumed by the flip-flops and the last branches of the clock distribution network that are driving the flip-flops [12]. So using lower clock frequency may translate into considerable power savings.Flip-flops thus contribute a significant portion of the chip area and power consumption to the overall system design. Therefore, it is imperative to carefully de...

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Section: Simulation Conditionsmentioning

confidence: 99%

“…This improved the power efficiency of the flip flop. The DET flip-flop shown in figure 4 was proposed by M. Pedram [16]. In this flip-flop the input data controls the passing of the clock signals in the feedback path of both data paths used in the circuit.…”

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confidence: 99%

Power Efficient Dual Edge-Triggered Storage Design

Khan¹,

Hasan²

2017

IJET

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“…The DET flip flop given in [1] is shown in figure 1. This flipflop is basically a Master Slave flip-flop structure and has two data paths.…”

Section: Conventional Double-edge Triggered Flip-flopsmentioning

confidence: 99%

Low Power and High Performance Detff Using Common Feedback Inverter Logic

.¹

2013

IJRET

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“…However, for sequential circuits flip-flop is the basic component and there remained ambiguity regarding the selection of appropriate timing parameters of flip-flop configurations till the last decade. The correct definition of flip-flop timing parameters was presented by Stojanovic and Oklobdzija (1999) which proposed data-to-output delay as the performance parameter and not clock-to-output delay unlike the previous works (Pedram et al, 1998). Moreover, power dissipation was also divided into three components internal power, clock power and data power.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

Singh¹,

Tiwari²,

Gupta³

2013

IJCAD

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This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.Keywords: VLSI; digital CMOS circuits; logical effort theory; Levenberg-Marquardt algorithm; power-delay product; power-delay-area product.Reference to this paper should be made as follows: Singh, K., Tiwari, S.C. and Gupta, M. (2013) 'A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits', Int.

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A new design of double edge triggered flip-flops

Cited by 58 publications

References 9 publications

Power Efficient Dual Edge-Triggered Storage Design

Power Efficient Dual Edge-Triggered Storage Design

Low Power and High Performance Detff Using Common Feedback Inverter Logic

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

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