A new design of mixed-voltage I/O buffers with low-voltage-thin-oxide CMOS process

Liu, Guijiang; Wang, Yuan; Jia, Shuang

doi:10.1109/icasic.2007.4415602

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Cited by 7 publications

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A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer

Kuo

Hou

Wang

2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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A PCI166-compatible 3×VDD mixed-voltage I/O buffer with ESD protection consideration is proposed. By using a compact Dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit sub-3×VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a Floating N-well circuit. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, with an equivalent probe capacitive load of 10 pF.

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