A new ECO technology for functional changes and removing timing violations

Abstract

Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage. We proposed a new approach to solve the function and timing problems simultaneously by rerouting the netlist to the spare cells. The proposed approach includes two stages (1) functional change with timing consideration and (2) timing optimization. In the first stage, a spare cell selection algorithm is designed to select proper spare cells which can solve the functional change problems with timing consideration. After the first stage, we conduct timing analysis to find paths which violated the timing constraints, and using gate sizing and buffer insertion techniques to remedy those paths. Experimental results are based on five industry benchmarks. The results show that our approach is effective and efficient in fixing the functional change problem and timing optimization problem.

Unified approach for simultaneous functional and timing ECO

“…Nonetheless, most previous studies have dealt with functional ECO and timing ECO separately. Few studies have sought to revise functional ECO and timing ECO simultaneously [15, 16]. As the revision manner is the same for both ECOs, an integrated ECO flow normally achieves better result in fixing wirelength and the success rate of ECO.…”

“…Another important issue of ECO is the resource competition for spare cells. Most previous researches have made use of greedy selection methods [2, 10] or matching algorithms [7–9, 11, 15, 16]. Matching algorithms are normally applied to bipartite graphs [17] for the assignment of elements from one set to another.…”

Timing-constrained replacement using spare cells for design changes

“…However, prior works only consider the functional or timing ECO problem. Recently, the functional and timing ECO problems in a complex design are concurrently considered in [3] [4]. However, both of their works neglect the timing effect due to spare cell rewiring such that timing violation may be generated after performing functional ECO.…”