A new efficient SC integrator scheme for high‐speed low‐power applications

Summary In this article, a low power time‐interleaved SAR (TI‐SAR) ADC is presented. Background calibration is used to improve the linearity of the ADC. Offset, gain, and capacitor mismatches between interleaved channels are calibrated by postprocessing the ADC output. Besides, a novel trimming‐based calibration algorithm is used to calibrate the timing mismatches between channels. The proposed calibration algorithm is more power‐efficient compared with most of its counterparts. The ADC consists of 18 parallel channels, a reference channel with two dummy channels, and a channel for timing calibration. The timing calibration channel is clocked only when the reference channel samples. The dummy channels are utilized to equalize the input load over time as they sample one after another to fill the gap where the reference channel does not sample. There is no need for any other dummy channels for timing calibration channel since it has low kickback noise over input driver. Each parallel channel operates at 111 ms/s while the reference channel runs at 105 ms/s. The aggregate sampling speed of the converter is 2 GS/s, and 52‐dB SNDR is accomplished near Nyquist frequencies.

Section: Noisementioning

confidence: 99%

Time‐interleaved SAR ADC design with background calibration

Adıyaman

Karalar

2020

“…Solution, corresponding to best value of objective function, is ranked first and is put on the top of solution archive. Every solution is assigned weights according to its rank, given by (1).…”

Section: Acomentioning

confidence: 99%

“…Best results obtained from optimization of CMOS buffer chain, Tpd-rise-ref = 583.53 ps, Tpd-fall-ref = 590.83 ps, Pavg-ref = 167.48 mW Range: k = (1,5) W/L = (1,80). Best results obtained from optimization of three input NAND gate, Td-ref = 70.40 ps, Pavg-ref = 18.37mW Range: W/L =(1,20).…”

mentioning

confidence: 99%

Transistor size optimization in digital circuits using ant colony optimization for continuous domain

Gupta

Ghosh

2012

In this paper, ant colony optimization (ACO) algorithm is presented, as a tool to find transistor sizes in digital circuits. Performance of ACO has been tested on four digital circuits, of different complexity, to find optimum balance between power and delay of circuits. Optimization problem has been set up by first, formulating an objective function, to be minimized, for each circuit and then finding the values of variables of circuits, using optimization algorithm. For the purpose of examining the results, circuits are optimized using genetic algorithm (GA) also. Results show that, ACO performs better than GA, for all the four circuits, in finding optimized transistor sizes.

“…Batteries and/or embedded energy harvesting transducers are used as the power source. SC delta-sigma ADCs [10][11][12][13][14][15][16] can also be one of the best choices in wireless sensor nodes by trading off the low power consumption, the small size, and the high resolution. The limited size and power consumption means that the requirement of the ADC resolution is loosened, and an 8-bit ADC generally satisfies the requirement for speech recognition and target tracking [2,8].…”

Section: Introductionmentioning

confidence: 99%

A 7.5‐μW 0.08‐mm² single‐ended SC delta‐sigma ADC for acoustic sensor applications

Duan

Wang

Roh

2015

This study presents an ultra-low-power, small-size, 1-bit, single-ended, and switched-capacitor (SC) deltasigma analog-to-digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta-sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low-power consumption. The chip area of the delta-sigma ADC is dominated by the capacitor; therefore, a novel common-mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm 2 in a 130-nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4-MHz sampling frequency and 0.7-V power supply voltage, the delta-sigma ADC achieves a 55.8-dB signal-to-noise-plus-distortion ratio (SNDR) and a 298-fJ/step figure-of-merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power.