A new era DFM solution for yield enhancement using machine learning (ML)

Abstract

The yield of the deep sub-micron semiconductor is secured by the process capability as well as the yield-friendly design capability. Yield-friendly design capabilities can be equipped with conventional Design for Manufacturability (DFM) that avoids already known defective layouts in design. Previously known defects can be defined as various rules and avoided in design, but defects that may occur at new technology nodes are difficult to avoid in advance. Indiscreetly defect-avoidance designs cause turn TAT increases and Power/Performance/Area (PPA) overheads in the design, which can ultimately lead to increased design costs and poor design competitiveness. The first step of this study is to predict potential risks and to specify major factor of risks that may occur at new process nodes with new DFM solutions developed using Machine Learning (ML) techniques. The second step is to secure early yield through avoidance design to prevent predicted defects and direct mask modification to improve defects. In this study, we present not only the introduction of new ML-based DFM solutions, but also the effect of predicting and improving defects through the application cases of real products.