2016
DOI: 10.1007/s10470-016-0845-7
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A new fast settling low power CMOS gain stage architecture

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“…Hence, high‐speed digital circuits are implemented in CML, which increases the power consumption of the proposed system. In order to provide a reasonable comparison, ‘Normalised power consumption [24]’ for each technology ( P N ) and the ratio of ‘ P N divided by frequency’ are calculated. Calculated P N values indicates that the proposed circuit in this work consumes around 16.32 mW (23%) less power in 0.18 μm technology compared with the normalised power of [11].…”
Section: Simulation Resultsmentioning
confidence: 99%
“…Hence, high‐speed digital circuits are implemented in CML, which increases the power consumption of the proposed system. In order to provide a reasonable comparison, ‘Normalised power consumption [24]’ for each technology ( P N ) and the ratio of ‘ P N divided by frequency’ are calculated. Calculated P N values indicates that the proposed circuit in this work consumes around 16.32 mW (23%) less power in 0.18 μm technology compared with the normalised power of [11].…”
Section: Simulation Resultsmentioning
confidence: 99%