A New FPGA-Based Segmented Delay-Line DPWM With Compensation for Critical Path Delays

Cheng, Xin; Cheng, Xin; Xie, Guangjun; Yu, Zhang; Zhang, Zhang

doi:10.1109/tpel.2017.2763750

Cited by 14 publications

(6 citation statements)

References 15 publications

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“…A diagram of the digital measurement system is illustrated in Fig. 19, and its key components are listed in Table IV The proposed methods for GPA resolution analysis and improvement are based on the noise gain models, mathematically presented by (31) to (35). Therefore, it is critical to validate the effectiveness of these built models in the GPA demonstrator.…”

Section: Resultsmentioning

confidence: 99%

“…In order to improve GPA and thus MRI resolution, both the quantization noise and the disturbances of the analog devices need to be suppressed. It can be observed in the resolution analysis equations that the noise gain models, defined in (31) to (35), play a critical role in resolution improvement. Moreover, the integration time T int in the integration function G int (f ) is of the order of a millisecond in MRI applications.…”

Section: A Bandwidth Optimization Methodsmentioning

confidence: 99%

“…In a full-digital PWM, T min is the minimum PWM counter time step which is determined by the PWM counter clock frequency and the number of externed asynchronous PWM bits [33]- [35]. Thus, (37) can also be represented with the PWM effective number of bits (ENOB) as follows:…”

Section: B Resolution Analysis For the Impact Of Quantizationmentioning

confidence: 99%

See 2 more Smart Citations

Resolution Improvement in a High-Power Magnetic Resonance Imaging Gradient Power Amplifier

Zeng

Popović

Rietveld

et al. 2022

IEEE Trans. Power Electron.

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High-resolution gradient power amplifiers are required to generate high-fidelity gradient fields in magnetic resonance imaging (MRI) systems. Various aspects of gradient power amplifiers have been the subject of research in the past years, however, systematic analysis and design methods for its resolution improvement have not been sufficiently addressed. This article addresses this research gap with comprehensive analysis and design methods for resolution improvement. First, a method for systematic resolution characterization of the MRI gradient power amplifier with gradient coil is proposed. Second, noise modeling with respect to the critical aspects in the system resolution degradation is developed and discussed. Third, the resolution improvement methods of bandwidth optimization, pseudorandom code modulation, and utilizing silicon carbide (SiC) switching power devices are proposed and analyzed, achieving a resolution at the one part in 10 6 level. Finally, the resolution improvement methods are experimentally validated in a 1000 V/400 A SiC gradient power amplifier. The experimental results show a 3.6 times reduction in the peak spurious signals and resolution improvement at all current levels and pulse lengths, compared to a conventional insulated gate bipolar transistor GPA. These results prove the validity of the proposed methods for resolution improvement in a high-power MRI gradient power amplifier, enabling future high-power and high-resolution amplifier designs.

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Section: Resultsmentioning

confidence: 99%

Section: A Bandwidth Optimization Methodsmentioning

confidence: 99%

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Resolution Improvement in a High-Power Magnetic Resonance Imaging Gradient Power Amplifier

Zeng

Popović

Rietveld

et al. 2022

IEEE Trans. Power Electron.

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show abstract

“…Cheng et al 19 compensated for the increased duty cycle by a software method, which added tool command language commands into synopsys design constraints (SDC) file. When different circuit structures or different types of device are used, the tool command language commands need to be modified accordingly, while the proposed HW method only needs to replicate the circuits in reset path which cause the additional delay to set path, thus balancing the delay between set path and reset path.…”

Section: The Proposed Dpwm Architecturementioning

confidence: 99%

“…Furthermore, the fine delay module existed in reset path of DPWM brings unavoidable interconnect delay and combinational logic delay and increases duty cycle of output signal, which is called duty cycle increment phenomenon in Cheng et al 19 However, none of the above designs focused on the duty cycle increment phenomenon, which also affected the regulation accuracy. Although Cheng et al 19 compensated for the increased duty cycle by a software method, it was difficult to transplant to different DPWM architectures or different hardware (HW) platforms which meant it lacked generality.…”

Section: Introductionmentioning

confidence: 99%

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

Cheng

Zhu

et al. 2020

Circuit Theory & Apps

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SummaryIn this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R2 is 0.99 and verify the effect of duty cycle compensation.

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A Digitally Controlled Delay Generator Implemented with Cyclone V FPGA Using Timing Analysis

Oliveira

Santos

Cajado

et al. 2023

Smart Innovation, Systems and Technologies

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A New FPGA-Based Segmented Delay-Line DPWM With Compensation for Critical Path Delays

Cited by 14 publications

References 15 publications

Resolution Improvement in a High-Power Magnetic Resonance Imaging Gradient Power Amplifier

Resolution Improvement in a High-Power Magnetic Resonance Imaging Gradient Power Amplifier

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

A Digitally Controlled Delay Generator Implemented with Cyclone V FPGA Using Timing Analysis

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