A new hardware architecture for sampling the exponential distribution

Ould-Bachir, Tarek; Sawan, Mohamad; Brault, Jean-Jules

doi:10.1109/ccece.2008.4564770

Cited by 7 publications

(11 citation statements)

References 10 publications

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“…Table I summarizes the major GVG and EVG architectures reviewed in this paper. As one can see, the design in [20] compares well with all the major designs even if it uses multiple LFSRs. Moreover, it doesn't make use of any multiplier and surpasses the designs in [16] in the effective area and BRAMs occupation.…”

Section: B Hardware Evgmentioning

confidence: 86%

“…An empirical analysis [13] showed that multiple (let us say k) w-bit LFSRs can be used in either a serial or parallel topology (the latter requires appropriate initial seeds) to form a PRNG with an enhaced random behaviour. This approach was successfully used in [19] and [20] but our implementation results showed a greedy ressource occupation: for instance, on Virtex II-Pro FPGA technology, the parallel topology (w = 32 and n = k · w = 1008) translates into an occupation of more than 1, 000 slices.…”

Section: A Hardware Implementation Of Uniform Prngmentioning

confidence: 99%

“…In [20], we proposed a new decision-tree technique for sampling the exponential distribution. Sections IV and V will review the algorithmic approach and the hardware architecture counterparts.…”

Section: B Hardware Evgmentioning

confidence: 99%

“…A similar algorithmic approach was later presented in [16] with two hardware counterparts that had a slight difference in their hardware implementations. The decisiontree technique translates into very efficient and high quality EVG hardware implementation [16], [20]. Table I summarizes the major GVG and EVG architectures reviewed in this paper.…”

Section: B Hardware Evgmentioning

confidence: 99%

“…The DT technique can be effectively implemented in hardware since all the bits can be generated in parallel [16], [20] and the bijective function x = T (a) is a simple fractional point shift.…”

Section: Decision-tree Techniquementioning

confidence: 99%

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FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods

Ould-Bachir

Brault

2009

2009 IEEE/ACS International Conference on Computer Systems and Applications

Self Cite

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Hardware acceleration in High Performance Computing (HPC) context is of growing interest, particularly in the field of Monte Carlo methods where the resort to Field Programmable Gate Array (FPGA) technology has been proven as an effective media, capable of enhancing by several orders the speed execution of stochastic processes. The spread-use of reconfigurable hardware for stochastic simulation gathered a significant effort towards effective implementations of hardware pseudorandom numbers generators (PRNGs) -these generators needed to exhibit a statistically proven random behaviour and to be charactarized by a very long period. In this paper we present the state of the art of hardware pseudorandom number generation in the context of Monte Carlo acceleration. We highlight the emerging trends over the most recent publications and suggest some insights on the forthcoming works. Furthermore, we provide a complete hardware description of a new gaussian variate generator (GVG) and an exponential variate generator (EVG) based on a decision-tree technique of ours, herein presented as well. The prototypes implemented on a Xilinx Virtex II Pro XC2VP100 FPGA occupy from 150 to 417 slices and reach 280 MHz, while exhibiting good statistical behaviours with high p-values on the χ 2 test and offering a unitary Knuth ratio.

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Section: B Hardware Evgmentioning

confidence: 86%

Section: A Hardware Implementation Of Uniform Prngmentioning

confidence: 99%

Section: B Hardware Evgmentioning

confidence: 99%

Section: B Hardware Evgmentioning

confidence: 99%

Section: Decision-tree Techniquementioning

confidence: 99%

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FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods

Ould-Bachir

Brault

2009

2009 IEEE/ACS International Conference on Computer Systems and Applications

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Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field‐Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk

Shoar

Zarandi

Nasirzadeh

et al. 2016

Quality & Reliability Eng

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This paper presents a stochastic logic-based method for quantitative risk assessment using fault tree analysis (FTA) that can take into account both types of uncertainties including objective and subjective uncertainties. In the proposed method, each fault tree gate is translated to its corresponding stochastic logic template and then is implemented on a field programmable gate array (FPGA). Because the analysis does not utilize any transformation methods, the results of analysis are more accurate than those methods which are based on transformation from possibility to probability distributions or vice versa. Experimental results for a benchmark fault tree show that this method accelerates analysis time compared to conventional hybrid uncertainty analysis method and transformation methods. The efficiency of the proposed method is demonstrated by implementation in a real steel structure project. The quantitative risk assessment is performed for the incomplete penetration as one of the defects encountered in arc welding process, and its results are compared with transformation methods. The comparison results show the proposed hybrid uncertainty analysis method is also more accurate in comparison to the transformation-based approaches.

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