A new high dynamic range moduli set with efficient reverse converter

Hariri, Arash; Navi, Keivan; Rastegar, Reza

doi:10.1016/j.camwa.2007.04.028

Cited by 58 publications

(67 citation statements)

References 14 publications

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“…From Fig. 1, it can be obtained the critical path is the timing path that propagates through the used (n + 1) × (n + 1) binary multiplier, the used n-bit CSA, n-bit binary adder (1), 5-bit binary adder, n-bit binary adder (2) and n-bit binary adder (3).…”

Section: The Feature Of Modulo (N + 3)mentioning

confidence: 99%

“…{2 n , 2 n − 1, 2 n + 1} is the most common used moduli set in RNS applications because they have lower implementation difficulty and computational complexity than other moduli forms, when considering the area × time 2 product, and also they can offer efficient converters from and to the binary system [1]. The novel moduli set {2 2n − 1, 2 n , 2 2n + 1} is studied [2]. The 4-modulus base set {2 n − 1, 2 n + 3, 2 n + 1, 2 n − 3} has been proposed [3,4].…”

Section: Introductionmentioning

confidence: 99%

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High-speed modulo (2n+3) multipliers

Zhou

2013

IEICE Electron. Express

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Section: The Feature Of Modulo (N + 3)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-speed modulo (2n+3) multipliers

Zhou

2013

IEICE Electron. Express

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“…There are many scientists dedicated to simplifying and accelerating the operation of Chinese remainder theorem to reduce the computation complexities in these applications. These works about parallelization of Chinese remainder theorem are mainly focused on fault-tolerant technology [2,3], binary reverse converter [4][5][6], distributed key distribution scheme [7,8] and fast encryption/decryption of cryptographic algorithm [9][10][11]. However, there is less deep study on more general parallel algorithms concerning multiple-precision integers for Chinese remainder theorem.…”

Section: Introductionmentioning

confidence: 99%

Fast Parallel Garner Algorithm for Chinese Remainder Theorem

Xiao

Liang

et al. 2012

Lecture Notes in Computer Science

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Abstract. This paper presents a fast parallel garner algorithm for Chinese remainder theorem. The variables in garner algorithm are divided into public parameters that are constants for fixed module and private parameters that represent random input integers. We design the parallel garner algorithm by analyzing the data dependencies of these arithmetic operations for computing public variables and private variables. Time complexities and speedup ratios of the parallel algorithm and the sequential algorithm are calculated to make the quantitative comparison based on our previous work about some fundamental parallel algorithms. The performance evaluation shows high efficiency of the proposed parallel algorithm compared to the sequential one.

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“…However, its dynamic range (DR) is not suitable for current highperformance DSP applications. To overcome this problem, i.e., having large DR together with the advantages of popular set {2 n , 2 n -1, 2 n +1}, Hariri et al [14] proposed the 5n-bit DR moduli set {2 n , 2 2n -1, 2 2n +1} with its high-speed and low-cost reverse converter. Moreover, the moduli set {2 α , 2 β -1, 2 β +1}, where α ≺ β, has been introduced by Molahosseini et al [15] to provide a large dynamic range RNS systems.…”

Section: Introductionmentioning

confidence: 99%

A General Reverse Converter Architecture with Low Complexity and High Performance

Navi

Esmaeildoust

Molahosseini

2011

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a general architecture for designing efficient reverse converters based on the moduli set {2 α , 2 2β+1 -1, 2 β -1}, where β ≺ α 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2 α , 2 2β+1 -1, 2 β -1} is free from modulo (2 k +1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {2 2n , 2 2n+1 -1, 2 n -1} which is a special case of the general set {2 α , 2 2β+1 -1, 2 β -1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {2 2n , 2 2n+1 -1, 2 n -1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {2 2n , 2 2n+1 -1, 2 n -1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR. key words: residue arithmetic, reverse converter, residue number system (RNS), VLSI architecture

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A new high dynamic range moduli set with efficient reverse converter

Cited by 58 publications

References 14 publications

High-speed modulo (2<I><SUP>n</SUP></I>+3) multipliers

High-speed modulo (2<I><SUP>n</SUP></I>+3) multipliers

Fast Parallel Garner Algorithm for Chinese Remainder Theorem

A General Reverse Converter Architecture with Low Complexity and High Performance

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