A New Hybrid 16-Bit*16-Bit Multiplier Architecture by m:2 and m:3 Compressors

Abstract

Abstract-Compressors are mostly used in multipliers to reduce partial products in a parallel manner. Firstly, this paper draw a comparison between the conventional m:2 and m:3 compressors. Secondly, a new hybrid 16-bit16-bit multiplier is proposed in this paper with the aim of taking benefits from both kinds of compressors. The new design decreases the amount of carry signals by employing m:3 compressors in the first stage. It also accelerates reducing partial products by using m:2 compressors in the following stages. The second and third phases of multiplication are considered together in this paper. The synthesizable structural VHDL code is used to simulate and implement different architectures. Our investigations demonstrate that the new multiplier is the fastest one with reasonable power and area dissipations.Index Terms-Compressor, m:2 compressor, m:3 compressor, full adder, half adder, hybrid architecture, multiplier, partial product reduction, ripple adder. I. INTRODUCTIONAs the feature size of transistors keeps shrinking, more and more complicated signal processing systems are being implemented on a single nano-scale chip. In today's IC design industry, interconnections have become a serious challenge because they occupy a large amount of the chip area and lead to restrictions in placement and routing of logic elements [1]. They consume a lot of power and cause parasitic effects by increasing the number of connections inside a chip. Wire capacitance can contribute up to 70% of the total chip capacitance [2], [3]. On the other hand, faster logic elements and arithmetic units have always been in high demand.Multiplication is considered as a rather complicated and time-consuming arithmetic operation. It is widely used in DSP algorithms such as filtering and Fourier transforms. It is also a fundamental computational unit in microprocessors, embedded systems, and crypto processors [4]- [7].Multiplier architecture is divisible into three phases [8]: partial product generation phase; partial product reduction phase; and the final addition phase. At first, partial products are produced by multiplying each bit of the multiplicand with each bit of the multiplier. This phase results in a huge number of partial products in different bit-weight positions. As a result, the partial product reduction is the most critical and time-consuming phase. All of the partial products must be accumulated up to the point where there are only two remaining partial products in each column. The final phase is the addition of these remaining partial products.A compressor is simply an adder circuit. It takes a number of equally-weighted bits, adds them, and produces some sum signals. Compressors are commonly used with the aim of reducing and accumulating a large number of inputs to a smaller number in a parallel manner. Their main application is within a multiplier, where a huge number of partial products have to be summed up concurrently. The inner structure of compressors avoids carry propagation. Either there are not any carry signa...

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

“…As a result, there is no difference which one becomes 'High' when the sum of input variables is two or three (Table I). In general, an (m:2) compressor requires m-3 input/output carries [17]. In binary logic, the (4:2) compressor is usually built by using two Full Adders (Fig.…”