A new hybrid fault detection technique for systems-on-a-chip

Bernardi, P.; Bolzani, L.; Rebaudengo, Maurizio; Reorda, Matteo Sonza; Vargas, F.; Violante, M.

doi:10.1109/tc.2006.15

Cited by 61 publications

(53 citation statements)

References 23 publications

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“…However, these approaches incur large performance, resource and energy overheads. Moreover, meeting shorter time-to-market requirements can be highly challenging as re-design and re-validation are required [1].…”

Section: Introductionmentioning

confidence: 99%

“…Using instruction-level parallelism at compiler-level the performance overheads can be reduced in this approach. A similar approach using instruction-level duplication technique for error detection in COTS DSP processors using multiple execution units has been proposed by Bernardi et al [1]. The duplicated executions in [1] are generated by hardware support units in the processor, which are then compared in a separate unit to detect errors.…”

Section: Introductionmentioning

confidence: 99%

“…A similar approach using instruction-level duplication technique for error detection in COTS DSP processors using multiple execution units has been proposed by Bernardi et al [1]. The duplicated executions in [1] are generated by hardware support units in the processor, which are then compared in a separate unit to detect errors. Pignol proposed another approach using task-level redundancy for error detection and tolerance in DMT and DT2 architectures [12].…”

Section: Introductionmentioning

confidence: 99%

“…Hardware and time redundancy approaches require direct hardware modification in the original system (such as, comparator design [1] or incorporating watchdog timers [13]). However, in many COTS based systems, adding or modifying hardware resources may not be feasible due to time-to-market and low design cost issues.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Software Modification Aided Transient Error Tolerance for Embedded Systems

Shafik

Rauwerda

Potman

et al. 2013

2013 Euromicro Conference on Digital System Design

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Abstract-Commercial off-the-shelf (COTS) components are increasingly being employed in embedded systems due to their high performance at low cost. With emerging reliability requirements, design of these components using traditional hardware redundancy incur large overheads, timedemanding re-design and validation. To reduce the design time with shorter time-to-market requirements, softwareonly reliable design techniques can provide with an effective and low-cost alternative. This paper presents a novel, architecture-independent software modification tool, SMART (Software Modification Aided transient eRror Tolerance) for effective error detection and tolerance. To detect transient errors in processor datapath, control flow and memory at reasonable system overheads, the tool incorporates selective and non-intrusive data duplication and dynamic signature comparison. Also, to mitigate the impact of the detected errors, it facilitates further software modification implementing software-based check-pointing. Due to automatic software based source-to-source modification tailored to a given reliability requirement, the tool requires no re-design effort, hardware-or compiler-level intervention. We evaluate the effectiveness of the tool using a Xentium R processor based system as a case study of COTS based systems. Using various benchmark applications with single-event upset (SEUs) based error model, we show that up to 91% of the errors can be detected or masked with reasonable performance, energy and memory footprint overheads.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Software Modification Aided Transient Error Tolerance for Embedded Systems

Shafik

Rauwerda

Potman

et al. 2013

2013 Euromicro Conference on Digital System Design

View full text Add to dashboard Cite

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“…Some recent works have shown the viability of this hybrid strategy [24,4]. In this context, there are needed suitable tools which allow the designer to easily explore the design space in order to find the best trade-off that satisfy the performance, reliability, and hardware cost requirements of a design.…”

Section: Introductionmentioning

confidence: 99%

A compiler-based infrastructure for fault-tolerant co-design

Restrepo-Calle

Martínez-Álvarez

Guzmán-Miranda

et al. 2010

Proceedings of the 13th International Workshop on Software &Amp; Compilers for Embedded Systems - SCOPES '10

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The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolatedfrom-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.

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Hybrid Techniques

Software-Implemented Hardware Fault Tolerance

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A new hybrid fault detection technique for systems-on-a-chip

Cited by 61 publications

References 23 publications

Software Modification Aided Transient Error Tolerance for Embedded Systems

Software Modification Aided Transient Error Tolerance for Embedded Systems

A compiler-based infrastructure for fault-tolerant co-design

Hybrid Techniques

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