A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays

Gyepes, Gábor; Stopjaková, Viera; Arbet, Daniel; Majer, Libor; Brenkuš, Juraj

doi:10.1016/j.micpro.2014.04.006

Cited by 8 publications

(2 citation statements)

References 22 publications

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“…Variations in quiescent supply currents have used to detect the faults [18]. Deviations in the transient current are used for the detection of the faults at block level [19]. The detection of bridging defects is discussed [20,21].…”

Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

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Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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“…Using exhaustive March tests to sensitize faults results in expensive manufacturing tests, as the test cost is directly related to the time each product stays on the tester [13]. Disparate approaches, such as monitoring the static or dynamic current consumption of SRAM cells [14][15][16][17], have been proposed to improve the detection of weak defects. Nevertheless, their efficacy regarding FinFET devices affected by resistive defects is unknown.…”

Section: Introductionmentioning

confidence: 99%

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Medeiros

Poehls

Taouil

et al. 2018

Microelectronics Reliability

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Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron technologies, as they may cause dynamic faults, which are hard to detect and therefore may increase the number of test escapes. This paper presents a defect-oriented test that uses On-Chip Current Sensors (OCCS) to detect weak resistive defects by monitoring the current consumption of FinFET SRAM cells. Using OCCS, all our single cell injected resistive defects have been detected within a certain accuracy by applying 5 read or write operations only, independent whether they cause static or dynamic faults. The proposed approach has been validated and the detection accuracy has been evaluated. Simulation results show that the approach is even able to detect weak resistive defects that do not even sensitize faults at the functional level, thus able to increase the reliability of devices.

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Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

Tak

Mali

2021

Lecture Notes in Electrical Engineering

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A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays

Cited by 8 publications

References 22 publications

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

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