A new latch comparator with tunable hysteresis

Khanfir, Leïla; Mouine, J.

doi:10.1109/icm.2016.7847865

Cited by 4 publications

(7 citation statements)

References 6 publications

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“…The hysteresis is analyzed and determined showing that the proposed design allows for accurate control without trading any circuit performance. On the other hand, the resulting circuit remains simple, effective, accurate and presents high performances compared to current works [15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 92%

“…Alternatively, ∆V 0O can be maintained at near 0 V values while adjusting ∆V 0X , as achieved in [16]. This technique allowed adjustment of hysteresis with good accuracy.…”

Section: Hysteresis In Latch Comparatorsmentioning

confidence: 99%

“…All these have achieved comparable hysteresis control ranges. However, the best energy efficiency was obtained when using dynamic CMOS circuits [16,17]. Although good accuracy was achieved in [16], the presented technique is geometry-dependent, and no external adjustment could be made.…”

Section: Introductionmentioning

confidence: 98%

“…However, the best energy efficiency was obtained when using dynamic CMOS circuits [16,17]. Although good accuracy was achieved in [16], the presented technique is geometry-dependent, and no external adjustment could be made. The work in [17] presents another solution that relies on the use of an advanced comparator structure and additional circuitry for clock delay control, which considerably increases the design complexity.…”

Section: Introductionmentioning

confidence: 98%

“…Current techniques for hysteresis control in static and dynamic comparators use Complementary Metal Oxide Semiconductor (CMOS) [10,[15][16][17], Floating-Gate MOS (FGMOS) [18], and Bipolar CMOS [19] silicon technologies. All these have achieved comparable hysteresis control ranges.…”

Section: Introductionmentioning

confidence: 99%

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Low-power latch comparator with accurate hysteresis control

Khanfir

Mouine

2020

Journal of Electrical Engineering

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Recent research has focused on finding ways to control hysteresis of dynamic comparators. The current proposed techniques are based on either geometrical dimension adjustment or digital control. The first case does not allow for post fabrication control, while the second has limited accuracy. This paper presents a new dynamic comparator design with external hysteresis adjustment using an analog voltage. This is achieved by proposing an architecture including control devices with a specific sizing. This is performed with no significant increase of the design complexity, keeping the power consumption as low as possible. The design is analyzed, showing that the proposed solution allows accurate hysteresis adjustment without affecting the inherent circuit properties. The dynamic comparator is also implemented using a 180 nm commercially available CMOS technology. The results show that a variation of 550 mV of the control voltage allows an accurate hysteresis adjustment ranging from 0 to 40 mV, according to the input conditions. Moreover, the simplicity of the circuit in conjunction with the use of dynamic technology have allowed the best performances to be achieved compared to the current state of the art, in terms of energy with an FoM equal to 116 fJ/decision and silicon area of 180 µm2 .

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Section: Introductionmentioning

confidence: 92%

“…Alternatively, ∆V 0O can be maintained at near 0 V values while adjusting ∆V 0X , as achieved in [16]. This technique allowed adjustment of hysteresis with good accuracy.…”

Section: Hysteresis In Latch Comparatorsmentioning

confidence: 99%