A new low power current steering logic circuit for the design of digital subsystem

Kumar, Mithilesh; Mondal, Abir J.

doi:10.1080/00207217.2021.1914188

Cited by 1 publication

(2 citation statements)

References 11 publications

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“…The P avg , t d and FoM are tabulated in comparison section highlighting performances deviation with present design. This work avoids the issue using a latch designed with a new current steering circuit [24]. It also accommodates structural adjustment to abstain output from deterioration due to fast slewing input and also to maintain full voltage swing.…”

Section: Literaturementioning

confidence: 99%

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An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

Kumar¹,

Mondal²

2023

RADIOENGINEERING

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Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (P avg ) trade-off in each era with power supply voltage (V dd ) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant P avg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage V P and overcharges output. In fact, V P is different than externally applied V dd and oscillates with time as and when an abrupt current is drawn. This affects delay t d and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (PDN). The significant point is to attain an almost constant t d in comparison to conventional designs while the V dd changes. The post-layout results at 0.09-μm CMOS and 1.1 V V dd indicate that the P avg and t d are 339.5 µW and 61.9 ps, respectively, at 27°C. Surprisingly, the t d variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when V P close to the circuit varies due to sudden current.

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Section: Literaturementioning

confidence: 99%

“…Latch built using two identical current steering circuits [24] and connected in a cross-coupled manner is shown in Fig. 3(b).…”

Section: Proposed Latchmentioning

confidence: 99%

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

Kumar¹,

Mondal²

2023

RADIOENGINEERING

View full text Add to dashboard Cite

show abstract

A new low power current steering logic circuit for the design of digital subsystem

Cited by 1 publication

References 11 publications

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

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