A New Memory Module for COTS-Based Personal Supercomputing

Tanabe, Noboru; Nakatake, M.; Hakozaki, H.; Dohi, Y.; Nakajo, Hironori; Amano, Hideharu

doi:10.1109/iwia.2004.10019

Cited by 11 publications

(9 citation statements)

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“…In order to improve performance for applications with discontinuous access in the conventional Intel-based PC, we proposed vector scatter and gather access functions on a memory module such as DIMMnet-2 [19,20]. This concept can be adopted for an AMD-based PC with an attached accelerator on a Hypertransport-based CPU socket such as Reconfigurable Processor Unit (RPU110) [9] made by DRC Computer Corporation.…”

Section: Memory Module With Vector Scatter and Gather Access Functionsmentioning

confidence: 99%

“…Tanabe named this buffer "window memory" in the previous proposed memory module, DIMMnet-1 [18]. Figure 2 shows the window memory with vector access functions on DIMMnet-2 [19,20].…”

Section: Memory Module With Vector Scatter and Gather Access Functionsmentioning

confidence: 99%

“…Our solution for these problems of COTS comprises vector load/store functions and capacity extensibility on a memory module such as DIMMnet-2 [19,20] or an attached accelerator on a CPU socket such as the DRC Reconfigurable Processor Unit (RPU110) [9]. Since, unlike Impulse, DIMMnet-2 does not suffer from the size limitation of CPU address space and no remanufacturing of a bridge chip is necessary, it can be utilized with a conventional COTS CPU, motherboard, and memory chip.…”

Section: Introductionmentioning

confidence: 99%

“…The basic concept of a memory module with vector load/store functions was proposed by Tanabe [19,20]. In Tanabe's work, the bandwidth effect was statically analyzed [19] and CG benchmark in small class (class B) for idealized hardware was evaluated [20] preliminarily.…”

Section: Introductionmentioning

confidence: 99%

“…In Tanabe's work, the bandwidth effect was statically analyzed [19] and CG benchmark in small class (class B) for idealized hardware was evaluated [20] preliminarily. The impulse memory controller was evaluated with CG in very small class (class A) by Carter [5].…”

Section: Introductionmentioning

confidence: 99%

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An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing

et al. 2009

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The performance of memory and I/O systems is insufficient to catch up with that of COTS (Commercial Off-The-Shelf) CPU. PC clusters using COTS CPU have been employed for HPC. A cache-based processor is far less effective than a vector processor in applications with low spatial locality. Moreover, for HPC, Googlelike server farms and database processing, insufficient capacity of main memory poses a serious problem. Power consumption of a Google-like server farm or a highend HPC PC cluster is huge. In order to overcome these problems, we propose a concept of a memory and network enhancer equipped with scatter and gather vector access functions, high-performance network connectivity, and capacity extensibility. Communication mechanisms named LHS and LHC are also proposed. LHS and LHC are architectures for reducing latency for mixed messages with small controlling data and large data body. Examples of the killer applications of this new type of hardware are presented. This paper presents not only concepts and simulations but also N. Tanabe ( ) 280 N. Tanabe et al. real hardware prototypes named DIMMnet-2 and DIMMnet-3. This paper presents the evaluations concerning memory issues and network issues. We evaluate the module with NAS CG benchmark class C and Wisconsin benchmarks as applications with memory issues. Although evaluation for CG class C is difficult with conventional cycle-accurate simulation methods, we obtained the result for class C with our original method. As a result, we find that the module can improve its maximum performance about 25 times more with Wisconsin benchmarks. However, the results on a cache-based PC show the cache-line flushing degrades acceleration ratio. This shows the high potential of the proposed extended memory module and processors in combination with DMA-based main memory access such as SPU on Cell/B.E. that does not need cache-line flushing. The LHS and LHC communication mechanisms are evaluated in this paper. The evaluations of their effects on latency are shown.

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Section: Memory Module With Vector Scatter and Gather Access Functionsmentioning

confidence: 99%

“…Tanabe named this buffer "window memory" in the previous proposed memory module, DIMMnet-1 [18]. Figure 2 shows the window memory with vector access functions on DIMMnet-2 [19,20].…”

Section: Memory Module With Vector Scatter and Gather Access Functionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%