A new method for precise evaluation of dynamic recovery of negative bias temperature instability

Aota, Shin-ichi; Fujii, Seizo; Jin, Zongshuai; Ito, Yasuaki; Utsumi, Kazuaki; Morifuji, E.; Yamada, Seiji; Matsuoka, F.; Noguchi, Toshihiko

doi:10.1109/icmts.2005.1452262

Cited by 8 publications

(4 citation statements)

References 2 publications

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“…Using DCIV, the density of the interface trap in p-MOSFETs can be precisely checked while transistors are under stress. A number of previous works [Chen et al 2002;Rangan et al 2003;Huard et al 2006;Aota et al 2005;Shen et al 2006;Ferńandez et al 2006] have employed a method that can probe current directly. Configurations based on ring oscillators were introduced in Kim et al [2008], Keane et al [2009], and Ketchen et al [2007].…”

Section: Measurement and Monitoringmentioning

confidence: 99%

Lifetime Reliability Enhancement of Microprocessors

Hong

Lim

et al. 2015

ACM Comput. Surv.

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Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues. ACM Reference Format:Hyejeong Hong, Jaeil Lim, Hyunyul Lim, and Sungho Kang. 2015. Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability.

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Section: Measurement and Monitoringmentioning

confidence: 99%

Lifetime Reliability Enhancement of Microprocessors

Hong

Lim

et al. 2015

ACM Comput. Surv.

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“…To accurately measure the effects of NBTI, this measurement must be done quickly to avoid the effects of recovery, which has been reported to occur even for measurement windows of a few microseconds [7]. On-the-fly techniques that minimize the recovery effect have been examined in [6], [7], [9], [13], [14], and [16]. Denais et al proposed a measurement technique in which the stress voltage is kept quasi-constant while the linear drain current is measured to monitor device degradation.…”

Section: Previous Reliabiltiy Monitoring Techniquesmentioning

confidence: 99%

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Kim

Persaud

Kim

2008

IEEE J. Solid-State Circuits

202

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Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 132 m 2 test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 s measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

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“…As discussed in previous sections, NBTI recovery was reported and explained within the frameworks of reaction-diffusion model [132], disorder-controlled-kinetics model [139], hole-trapping model [80,154,155] and deep-level hole-trapping model [161,162,[164][165][166], and it was also widely observed by other researchers [40,77,79,152,[167][168][169][170]. NBTI recovery could be closely associated with re-passivation of interface traps and hole de-trapping of oxide traps.…”

Section: Models For Nbti Recoverymentioning

confidence: 83%

“…As reviewed in Chapter 2, NBTI recovery phenomenon was widely observed and reported [40,77,79,152,[167][168][169][170]. In Chapter 3, some experimental investigations of ATTENTION: The Singapore Copyright Act applies to the use of this document.…”

Section: Physical Modeling Of Nbti Recovery and Dynamic Nbtimentioning

confidence: 99%

Characterization and modeling of negative bias temperature instability in P-MOSFETs

Yang¹

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It has been the intent of this work to investigate negative bias temperature instability (NBTI) in p-MOSFETS with ultra-thin nitrided gate oxides experimentally and theoretically. A systematic study on NBTI has been carried out and the understanding of NBTI mechanism is further enhanced. Firstly, a simple NBTI characterization technique of measuring a single-point saturation drain current has been proposed to minimize the unfavorable NBTI recovery during measurement. With this method, the measurement time can be largely reduced. This method gives a closer-to-real threshold voltage shift and thus yields a more reliable power-law factor. Subsequently, since NBTI has become a key device reliability challenge for advanced CMOS technology nodes, an NBTI in-line test methodology has been developed to monitor NBTI during the device development phase. Moreover, NBTI recovery is experimentally examined, and a combined empirical model for NBTI recovery within the modulated measurement time frame has been proposed to describe the entire process of NBTI recovery in a wide time range. A comprehensive study on the modeling of NBTI has been conducted. An analytical reaction-diffusion (R-D) model within the framework of the standard R-D model has been developed. This model can well describe NBTI in a wide time scale covering the three regimes of reaction, transition and diffusion. A power-law factor of ~1 is experimentally observed for the nitrided gate oxide, which shows clear evidence of the existence of the reaction-limited regime for NBTI. The analytical R-D model

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A new method for precise evaluation of dynamic recovery of negative bias temperature instability

Cited by 8 publications

References 2 publications

Lifetime Reliability Enhancement of Microprocessors

Lifetime Reliability Enhancement of Microprocessors

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Characterization and modeling of negative bias temperature instability in P-MOSFETs

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