A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Tsai, Kuen-Yu; You, Meng-Fu; Lu, Yi-Chang; Ng, Philip C. W.

doi:10.1109/iccad.2008.4681587

Cited by 2 publications

(4 citation statements)

References 11 publications

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“…The Location-Dependent Weighting Factors (LDWFs) method [10]- [12] can compensate for the current density variation caused by narrow width effects. The weightings are extracted from various non-rectangular gate devices through 2D and 3D TCAD simulations.…”

Section: 4 Location-dependent Weighting Factors Methodsmentioning

confidence: 99%

“…The segment whose slice length (Lslice) is less than 10 nm will be discarded due to the limit of the SPICE model. The location-dependent weighting factors and TCAD modeling [10]- [12] will be introduced in the future for more accurate evaluation.…”

Section: Slicing Methods Of Channel Region For Equivalent Gate Length...mentioning

confidence: 99%

“…We can see that the estimated Pstatic of the EGLoff method has a larger discrepancy. The LDWFs [10]- [12] are necessary to improve the error ratio since the off-state current is sensitive to gate length variation. Figure 19 shows the trade-off curve with the EGLon method.…”

Section: Accuracy Of Different Egl Methods W/o Ldwfsmentioning

confidence: 99%

“…The previous study indicates that the EGLoff and Min. NMSE method with LDWFs perform better than other methods especially in the off-state characteristic and static power analyses [10]- [12] .…”

Section: Equivalent Gate Length Extraction Techniques and Current Tab...mentioning

confidence: 98%

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A transistor sizing method for standard-cell optimization considering lithography effects

Cai,

Su,

Lee

et al. 2024

DTCO and Computational Patterning III

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In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.

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Section: 4 Location-dependent Weighting Factors Methodsmentioning

confidence: 99%

Section: Slicing Methods Of Channel Region For Equivalent Gate Length...mentioning

confidence: 99%