A new methodology for board-level harmonic analysis of multi-level packages

Abstract

Design of multi-level packages for better reliability life under drop impact is often conducted through board-level drop testing. Among many failure modes associated with the board-level drop impact test, PCB pad cratering and solder joint disconnection are of particular interests. Because of the complexity and rigor in modeling and simulations, most of the present work is completed through design of experiments under a variety of board-mounting layouts and drop criteria, in order to acquire information specific to a design of interest. A new methodology is proposed to model complicated boardlevel drop impact by using the receptance theory. Receptance is defined as the ratio of a displacement response at a place to a harmonic load which is applied at the same or different place.This modeling technique enables systematically dynamic coupling and spatial coupling of the mounting board and packages. The first part of this paper is on the formulation of board-mounted multi-level packages at various locations of the mounting board, together with a solution process for the natural frequencies and vibration modes of the integrated system. Then numerical results are presented to predict the response of the assembly, and emphasis is placed on (1) the force (deformation) in the interconnections at each level between the PCB pad and packages, (2) the effect of the package's mounting location on the stresses in the solder interconnects at each level, and (3) the size effect of packages and interconnects on the deformation of interconnections at each level. The technique to be demonstrated can facilitate selection of design parameters such as the solder materials, package's mounting locations, as well as the dimensions of the mounting board, before rigorous experiments and detailed simulations. IntroductionThe design of stacked scale packages (S-CSPs) allows for better use of space for high-density packaging [1], such as the example shown in Figure 1. Among a few known reliability issues the solder interconnects in S-CSPs are vulnerable to high-stress loading, which is unavoidable under drop impact or thermal shock. To better understand the stress-driven reliability issue in the stacked packages, this paper is aimed at developing a theoretical framework for capturing the known influence factors observed in board-level drop impact testing.