A New Model for Series Resistance of Amorphous Silicon Thin Film Transistor

Abstract

We presents a new model for the series resistance of an amorphous silicon (a-Si) thin film transistor (TFT) with an inverted-staggered configuration, considering the current spreading under the source and the drain contacts as well as the space charge limited current. The calculated results of our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the relative contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which has been verified successfully by the experimental measurements.