A new motion estimation core dedicated to H.263 video coding

Fujita, Gen; Onoye, Takao; Shirakawa, Isao

doi:10.1109/iscas.1997.622018

Cited by 19 publications

(9 citation statements)

References 4 publications

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“…The proposed architecture has been compared with 5 different block-based motion estimation architectures [12][13][14][15][16]. There are two differences between the proposed architecture and the published architectures in [12][13][14][15][16]:…”

Section: Prototyping and Performance Analysismentioning

confidence: 99%

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A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices

Sayed

Badawy

2005

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a Computational Memory architecture for MPEG-4 applications with mobile devices. The proposed architecture is used for real-time block-based motion estimation, which is the most computational intensive task in the video encoder. It uses the exhaustive block-matching algorithm (EBMA) for motion estimation. The proposed architecture consists of embedded SRAMs and a number of block-matching units working in parallel to process video data while stored in the memory. The block-matching units access the embedded SRAMs simultaneously, which increases the speed of the architecture.The architecture processes CIF format video sequences (i.e., the frame size is 352 × 288 pixels) with block size of 16 × 16 pixels and ±15 pixels search range. The proposed architecture has been designed, prototyped, and simulated for 0.18 µm TSMC CMOS technology. The simulation shows that the proposed architectures processes up to 126 CIF frames per second with clock frequency 100 MHz. The synthesized prototype of the proposed architecture includes 200 KB memory and it has an area of 33.75 mm 2 and consumes 986.96 mW @100 MHz.

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Section: Prototyping and Performance Analysismentioning

confidence: 99%

“…The architectures in [12][13][14][15][16] have off-chip memory, whose silicon area and power consumption are not included while the proposed architecture has only on-chip memory. 2.…”

Section: Prototyping and Performance Analysismentioning

confidence: 99%

A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices

Sayed

Badawy

2005

J VLSI Sign Process Syst Sign Image Video Technol

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“…The detailed description of the chip specification is listed in Table VI. A brief comparison with some FSBM motion-estimation chips is given in Table VII. G. Fujita [5] designed for H.263 and H. D. Lin [10] designed for H.261. The clock rate shown here is the working frequency for real-time application.…”

Section: Implementation and Comparisonmentioning

confidence: 99%

“…For real-time application, either dedicated hardware or a fast algorithm should be applied. Nowadays, there are many fast algorithms for block-matching motion estimation, such as a three-step hierarchical search [2], 1-D full search [3], 2-D logarithmic search [4], clustering search [5], and sub-sampled search [6] … etc., but the degradation of the picture quality and the irregular data flow make it less attractive in system view. On the other hand, due to the amazing progress of IC fabrication technique, a full-search algorithm could be efficiently implemented in a video system.…”

Section: Introductionmentioning

confidence: 99%

A novel low-power full-search block-matching motion-estimation design for H.263+

Shen

Wang

Chen

2001

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-In this paper, a low-power full-search block matching (FSBM) motion-estimation design for ITU-T recommendation H.263+ standard was proposed. New motion-estimation modes in H.263+ can be fully supported by our architecture. Unlike most previously presented motion-estimation chips, this design can deal with 8 8 and 16 16 block size with different searching ranges. Basically, the proposed architecture is composed of an integer pixel unit with 64 processing elements, and a half-pixel unit with interpolation, a control unit, and data registers. In order to minimize power consumption, gated-clock and dual-supply voltages are used. This design has been realized by TSMC 0.6 m SPTM CMOS technology. The power consumption is 423.8 mW at 60 MHz and the throughput is 36 fps in CIF format.

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“…A compact ME core (Fujita, 1997) Figure 3 Organization of ME core The H.263 standard supports the PB-frame…”

Section: Organizationmentioning

confidence: 99%

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

Miki

Fujita

Kobayashi

et al. 1997

VLSI: Integrated Systems on Silicon

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A number of novel VLSI architectures are devised for an H.263 video codec core in terms of low bitrate visual communication. The potential of the practicability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 mm 2 by means of a 0.35m CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.

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A new motion estimation core dedicated to H.263 video coding

Cited by 19 publications

References 4 publications

A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices

A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices

A novel low-power full-search block-matching motion-estimation design for H.263+

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

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