A new multi-finger SCR-based structure for efficient on-chip ESD protection

A novel and robust un-assisted positive and negative operations are higher than 60 mA/,um, low-trigger and high-holding voltage silicon controlled thus enabling excellent ESD protection levels of ± 8 kV rectifier (uSCR) is proposed and realized in a 0.35-,um human body model (HBM) and ± 2 kV charged device fully-salicided BiCMOS process. Without using any model (CDM) based on the joint electron device external trigger circuitry, the uSCR has a trigger engineering council (JEDEC) standard.voltage as low as 7 V to effectively protect deep submicron MOS circuits and a holding voltage higher II. DEVICE STRUCTURE than the supply voltage to minimize transient influence and avoid latch-up issue. Moreover, the electrostaticThe device cross-section view of the uSCR is shown discharge (ESD) protection robustness of the uSCR in in Fig. 1. In a typical low-triggering SCR without an both positive and negative operations exceeds 60 external trigger circuit [7], the blocking junction that mA/,um, which enables ESD protection levels of 8 kV controls the trigger voltage is the N+/P-Well junction in human body model (HBM) and 2 kV charged device Fig. 1. In order to develop the novel uSCR to reach very model (CDM) for a low voltage ICs, while each uSCR low trigger voltage, the N-type ESD (NESD) and P-type cell only consumes an area of about 2400 rmt lightly-doped drain (PLDD) regions (regions indicated with dashed lines in Fig. 1) are added into the

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A novel low-trigger and high-holding voltage SCR without externally- assisted circuitry for area-efficient on-chip ESD protection

Lou

Liou

2007

2007 International Semiconductor Device Research Symposium

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A new multi-finger SCR-based structure for efficient on-chip ESD protection

Cited by 6 publications

References 4 publications

Silicon controlled rectifier (SCR) compact modeling based on VBIC and Gummel–Poon models

Silicon controlled rectifier (SCR) compact modeling based on VBIC and Gummel–Poon models

A Novel and Robust Un-Assisted, Low-Trigger and High-Holding Voltage SCR (uSCR) for Area-Efficient On-Chip ESD Protection

A novel low-trigger and high-holding voltage SCR without externally- assisted circuitry for area-efficient on-chip ESD protection

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