A new NAND-type flash memory package with smart buffer system for spatial and temporal localities

Lee, Jung‐Hoon; Park, Gi-Ho; Kim, Shin-Dug

doi:10.1016/j.sysarc.2004.10.002

Cited by 29 publications

(15 citation statements)

References 8 publications

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“…In those conditions (Random worst case column of The researches on how to use NAND to execute code can be classified in four categories. First, we can distinguish pure hardware solutions since NAND is not a well-adapted device to do it [4,5,6,7]. On the opposite, some researchers [8,9,10,11,12,13,14,15] proposed software solutions using already available NAND, even if, here, software is often limited to firmware.…”

Section: Motivation Around Smart-card and Flash-memories Characteristicsmentioning

confidence: 99%

Key-Study to Execute Code Using Demand Paging and NAND Flash at Smart Card Scale

Cogniaux

Grimaud

2010

Lecture Notes in Computer Science

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International audienceNowadays, the desire to embed more applications in systems as small as Smart Cards or sensors is growing. However, physical limitations of these systems, like very small main memory, and their cost of production make it very difficult to achieve. One solution is to execute code from a secondary memory, cheaper, denser, but slower, as NAND Flash. Solutions based on Demand Paging and using a cache in main memory, began to be proposed and implemented in the domain of mobile phones, but consume too much RAM yet, compared to what a Smart Card can provide. In this paper, we show that we can dramatically increase performance by reducing the size of pages in the cache. This solution then allows a more intelligent access to the NAND. We also show that our solution allows to use Demand Paging within the limits of Smart Cards memories, where a conventional approach, offering too low bandwidth, makes code execution impossible from this kind of secondary memory. Finally, we present important future keys to optimize our proposal even more, and specially off-line code specialization aware of NAND characteristics and advanced cache properties

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Section: Motivation Around Smart-card and Flash-memories Characteristicsmentioning

confidence: 99%

Key-Study to Execute Code Using Demand Paging and NAND Flash at Smart Card Scale

Cogniaux

Grimaud

2010

Lecture Notes in Computer Science

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“…Lee et al [11] proposed a NandFlash package with a smart buffer system based on the spatial and temporal localities. The temporal locality refers to the probability that recently accessed data will be accessed again in the near future.…”

Section: Related Workmentioning

confidence: 99%

“…n is the number of bytes to be accessed from/to the buffer, m is the number of pages to be written to NandFlash when the buffer is not enough, and l is the number of pages to be read from NandFlash to the buffer as read miss. The NandFlash R/WB designed by Jo et al [10] and Lee et al [11] is shown in Figure 3. In a write operation, the host first stores data in the buffer.…”

Section: Definition Of the Energy Consumption Of A Nandflash Storage mentioning

confidence: 99%

A New Adaptive Grey Decision-Energy Aware Management System Based On The Optimal Read Only-Write Buffer Architecture For Flash Memory In Embedded And Mobile Devices

Huang¹,

Chen²,

Jeong³

et al. 2010

Intelligent Automation & Soft Computing

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It is generally accepted that the trends in ubiquitous and pervasive computing are rapidly increasing the diversity and heterogeneity of wireless technologies and their constituent devices. However, there are significant problems to overcome when integrating embedded and mobile devices into a ubiquitous and pervasive computing environment. One can consider that flash memory is an essential storage medium for embedded and mobile devices, because it is small, lightweight, nonvolatile, and vibration-resistant; and it has a high storage capacity. Lower energy consumption is an important consideration in the design, and one solution for reducing energy consumption is to include a buffer layer in a flash memory storage system. A buffer layer can let data be updated in situ, reduce energy consumption, and increase access performance. We developed an optimal-read only-write buffer architecture tailored to the properties of flash memory, since a traditional read/write buffer architecture is unsuitable for flash memory. Further, we propose an adaptive grey decision policy for considering temporal and spatial localities to obtain better results. Our proposed method shows that the number of flash memory write operations to reduce energy consumption is decreased from 15% to 35% compared to the least recently used and flash-aware buffer policies based on the optimal-read only-write buffer architecture. * Corresponding author. Postal address: 16 Danghyun 2-gil, Nowon-gu, Seoul, 139-791, South Korea. Tel.: +82 10 6289 8848; fax: +82 2 950 5408.

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“…Even though modern SSDs outperform HDDs, many research works continue to pursue further increases in their performance from the architectural perspective. Lee et al proposed a new NAND Flash memory package with smart buffer cache for exploiting the spatial and temporal localities [1]. Park et al proposed an energy aware demand paging using Clean First LRU algorithm which minimizes the number of write or erase operations [2].…”

Section: Introductionmentioning

confidence: 99%

Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs

Bang

Park

et al. 2009

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a Solid-State Disk (SSD) with a Double Data Rate (DDR) DRAM interface for high-performance PCs. Traditional SSDs simply inherit the interface protocol of Hard Disk Drives (HDD) such as Parallel Advanced Technology Attachment (PATA) or Serial-ATA (SATA) for maintaining the compatibility. However, SSD itself provides much higher performance than HDD, hence the interface also needs to be enhanced. Unlike the traditional SSDs, the proposed SSD with DDR DRAM interface is placed in the North Bridge which provides two or more DDR DRAM interface ports in high-performance PCs. The novelty of our work is on DQS signaling scheme which allows arbitrary Column Address Strobe (CAS) latency unlike typical DDR DRAM interface scheme. The experimental results show that the proposed SSD maximally outperforms the traditional SSD by 8.7 times in read mode, by 1.5 times in write mode. Also, for synthetic workloads, the proposed scheme shows performance improvement over the conventional architecture by a factor of 1.6 times.

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A new NAND-type flash memory package with smart buffer system for spatial and temporal localities

Cited by 29 publications

References 8 publications

Key-Study to Execute Code Using Demand Paging and NAND Flash at Smart Card Scale

Key-Study to Execute Code Using Demand Paging and NAND Flash at Smart Card Scale

A New Adaptive Grey Decision-Energy Aware Management System Based On The Optimal Read Only-Write Buffer Architecture For Flash Memory In Embedded And Mobile Devices

Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs

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