A new offset cancellation technique for CMOS differential amplifiers

Abstract

A new offset cancellation ~e c h n~~u e for CMOS tial amplifiers is presented where the input offset is reduced by a factor set by the voltage gain in a f~~d b~c~ loop. This approach does not require any active and D/A converters, and can be utilized in the design of operational amplifiers and voltage comparators built in a standard CMQS technology. The input offset voltage is constantly adjusted for improved time and temperature stability. The effect of clock feedthrough voltage on the input offset is reduced by employing a new low frequency clocking scheme with long rise and fall times. Continuous operation is achieved by using B parallel processing configuration where two amplifiers operate sequentially for half of each clock period.Power consumption and die area are considerably lower than any other method with equivalent performance.

A high gain low offset amplifier with rail-to-rail inputs

“…In comparison with bipolar ones, one of the important drawbacks is the high input offset voltage. Typically, the value could be as high as 2OmV [1]. Thus, a bipolar differential input stage is used here to obtain low input offset.…”