A new partitioning method for parallel simulation of VLSI circuits on transistor level

Abstract

Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transistor level with highly accurate element modelling, long simulation runtimes of typically several hours delay the design process. One possibility to reduce these runtimes is to divide the circuit into several partitions and to simulate the partitions in parallel. But the success of such a parallel simulation is heavily depending on the quality of the partitioning. This paper presents a new approach for partitioning VLSI circuits on transistor level and gives runtimes of parallel simulations of large industrial circuits. The resulting runtimes show considerable improvement compared to a known partitioning method, the Node Tearing method [10].

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

“…The connection network calculation is time consuming, and simulation runtime increases with each additional interconnecting signal between the partitions [14]. The partitioning algorithm also creates a master partition that takes care of the consistency of the circuit variables at the connections and accommodates local time agents to the main simulation time agent for all subcircuits.…”

“…TITAN uses a complex partitioning algorithm COPART to split the circuit description and distribute generated partitions to different workstations/processors. The partitioning is based on evaluating the level of coupling between adjacent elements, and the generated partitions (SPICE subcircuits) tend to have small number of interconnect nodes and well-balanced sizes [14]. Partitioning cuts the nets between partitions, that is, interconnect nets.…”

“…The master process evaluates the network variables within the connection network while the slave processors wait (that is, stop the parallel simulation). The connection network calculation is time consuming, and simulation runtime increases with each additional interconnecting signal between the partitions [14].…”

Genetic Algorithms for Applied CAD Problems

“…One of major OTDM is to partition the graph into a given or any number of parts [75,[77][78][79][80][81][82][83][84]. The task of graph partitioning has many practical applications.…”