A New Process for On-Chip Inductors with High Q-Factor Performance

Abstract

A novel technological method to improve the quality factor (Q) of RF-integrated inductors for wireless applications is presented in this paper. A serious reduction of substrate losses caused by capacitive coupling is provided. This is realised by removing the oxide layers below the coils with optimized underetching techniques. This special etching procedure is used to establish an environment in the inductor substructure with very low permittivity. A set of solid oxide-metal-columns placed below the metal windings stabilize the coil and prevent the hollowed out structure from mechanical collapse. The oxide capacitance is lowered significantly by the reduction of the permittivity from values around 4 to nearly 1. Capacitive coupling losses into substrate are decreasing in the same ratio. The resulting maximum Q-factors of the new designs are up to 100% higher compared to the same devices including the oxide layers but shifted significantly to higher frequencies. Improvements of Q from 10 up to 15 have been obtained at a frequency of 3 GHz for a 2.2 nH inductor with an outer diameter of 213 m. The resonance frequency () and frequency at maximum Q () are shifted to higher frequencies, caused by the shrunk total capacitance of the structure. This enables the circuit designer to use the inductors for applications working at higher frequencies. Coils with different layouts and values for inductance (L) were verified and showed similar results.

High frequency microwave on-chip inductors using increased ferromagnetic resonance frequency of magnetic films

“…6c. The de-embedded scattering parameters from the VNA are converted to inductance, L, and quality factor, Q, at each frequency, f [8,14].…”

Analytic Design of on-Chip Spiral Inductor with Variable Line Width

“…It is well known that the Q-factor of a Si-based spiral inductor is mainly determined by three technology parameters: (1) the resistive loss of the metal line, (2) the substrate loss of the silicon buck, and (3) the parasitic capacitance of the insulating oxide layers. By using advanced micromachining technologies, various novel spiral structures have been proposed to alleviate the loss of silicon substrate and the parasitic oxide capacitance [1][2][3][4][5][6][7][8][9][10][11][12][13]. In general, these designs can greatly improve the Q-factor of RFIC inductors, but they can be much more expensive than designs using standard silicon technology.…”

Running inductance of cylindrical conductors with axial current density

“…The study of [3] brings to idea that running inductance inserts the major contribution into the inductance of conductor.…”