A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

Kumar, Ankur; Nagaria, R. K.

doi:10.1007/s10470-019-01473-3

Cited by 15 publications

(2 citation statements)

References 26 publications

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“…To minimize power dissipation, many researchers have proposed different ideas from the device level to the architectural level [1]. There are numerous methods discussed to reduce leakage power in CMOS based circuit designing [2][3][4][5][6][7][8][9][10]. Each approach delivers a novel way to reduce leakage power, but the shortcomings of each approach limit the claim of each approach to be the best.…”

Section: Introductionmentioning

confidence: 99%

“…Pdynamic = α .CL.Vdd 2 .fclk (2) In this manuscript, a new low-power reduction approach is proposed, which provides an innovative choice for low-power VLSI designers/engineers to reduce leakage current in a much better way besides increasing in area and delay to a small extent. An unbiased comparison of the proposed approach with previously available low-power approaches is made in estimating the accuracy of the proposed approach.…”

Section: Introductionmentioning

confidence: 99%

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Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

Kassa¹,

Misra²,

Nagaria

2021

FACTA U EE

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Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

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