A new reactive processor with architectural support for control dominated embedded systems

Roop, Partha S.; Salčić, Zoran; Biglari-Abhari, Morteza; Bigdeli, Abbas

doi:10.1109/icvd.2003.1183135

Cited by 3 publications

(3 citation statements)

References 8 publications

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“…As mentioned in the introduction, the only other reactive processor proposals in the sense of Esterel that we are aware of are the ReFLIX and RePIC designs [17,18,9], of which RePIC is the more advanced. The RePIC includes an abort handling block, which is used for handling both strong and weak aborts; it does not handle suspension.…”

Section: Related Workmentioning

confidence: 99%

“…So far, there have been only limited and fairly recent investigations of the reactive processor approach. To our knowledge, the ReFLIX and RePIC architectures proposed by Dayaratne, Roop, Salcic et al [17,18,9] are the only ones that fall into this category, and they both follow the patched processor strategy. Their results are fairly promising, illustrating the potential of this approach.…”

Section: Introductionmentioning

confidence: 99%

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An Esterel processor with full preemption support and its worst case reaction time analysis

Lukoschus

Boldt

et al. 2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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The concurrent synchronous language Esterel allows programmers to treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-synchronous high-level languages, such as VHDL or C, and then compiled further into hardware or software. Another approach that has been proposed recently is the direct execution of Esterel-like instructions with a customized processor, which promises the flexibility of a software solution with an efficiency close to a hardware implementation. However, the instruction sets and implementations of the processor architectures proposed so far still have some limitations regarding their completeness, efficiency, and adherence to the original Esterel semantics. This paper presents a novel reactive processor architecture, the Kiel Esterel Processor, which addresses these shortcomings. In particular, it provides a complete, semantically accurate implementation of the Esterel preemption primitives, most of which can be expressed directly with a single machine instruction. One advantage of the reactive processors-in addition to their high execution speed compared to traditional software implementations-is that control-flow is preserved while compiling Esterel into machine code, and that the execution platform has a very predictable timing behavior. This paper presents a precise and very efficient Worst Case Reaction Time (WCRT) analysis, which is geared towards the Kiel Esterel Processor, but which could be adapted to other reactive processors as well.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Esterel processor with full preemption support and its worst case reaction time analysis

Lukoschus

Boldt

et al. 2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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“…Such systems must carefully manage priority of processed events and they use special architectures to achieve that [4]. • Data-dominant embedded systems typically consist of architecture optimized on effective data operations and transfers.…”

Section: Introductionmentioning

confidence: 99%

Knowledge Based Embedded System Modeling With Real-Time Response Requirements

Zeleznik¹,

Havlice²

2012

IJCTE

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The paper presents a proposal of a hybrid method for embedded system modeling with emphasis on constraints analysis. Since one of the major factors for most embedded system from the performance point of view is the real-time response of component execution the proposed method focuses on analysis of attributes affecting such performance requirements and optimizes the design process accordingly. The core idea of the method is to separate components into three distinctive groups as critical, hybrid and non-critical and select an appropriate memory and resources sharing model accordingly. Experimental case study is provided to verify the method performance compared to other available modeling methods like best-effort or dependable embedded system design methods. The hybrid method shows its advantages in more effective use of available implementation platform resources while meeting all of the required real-time response constraints.

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