A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Sterpone, Luca; Violante, M.

doi:10.1109/tc.2006.82

Cited by 135 publications

(81 citation statements)

References 22 publications

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“…• Placement and Routing Tools: These tools physically place and map the application design to the physical resources of the FPGA [5], [6].…”

Section: Fpga Features Used For Ftmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

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Abstract-Thedynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.

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“…• Placement and Routing Tools: These tools physically place and map the application design to the physical resources of the FPGA [5], [6].…”

Section: Fpga Features Used For Ftmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

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“…However, they do not guarantee complete protection of faults inside SRAMbased FPGAs. For solving this problem, a specific reliability-oriented place and route algorithm (RoRA) has been developed [10]. RoRA is an attractive solution for SRAM-based FPGAs because it introduces full hardware redundancy in the user's combinational and sequential logic, the routing signals and the I/O pads and it guarantees complete protection against SEUs affecting the FPGA's configuration memory [11].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Some preliminary works describing these tools have been presented in [9] and [10]. In this paper we present new versions of both the algorithm.…”

Section: The Star-discovery/rora-lx Tool Chainmentioning

confidence: 99%

“…The RoRA-LX place and router is an enhanced version of the RoRA algorithm that has been introduced in [10] to solve the problem of crossing error domains of the Triple Modular Redundancy techniques. Basically, the RoRA algorithm routes each connection between two logic components through the shortest path it can find.…”

Section: Rora-lxmentioning

confidence: 99%

“…The path is composed of routing Programmable Interconnection Points (PIPs). During path selection, RoRA labels dynamically the routing PIPs, in such a way that it avoids the routing of two connections that may be subject to Short effects or Multiple Opens effects as clearly illustrated in [10].…”

Section: Rora-lxmentioning

confidence: 99%

See 2 more Smart Citations

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

Sterpone¹,

Aguirre²,

Tombs³

et al. 2008

2008 Design, Automation and Test in Europe

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FPGAPALDesign Tools

Sterpone

2009

Wiley Encyclopedia of Computer Science and Engineering

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Reconfigurable logic devices such as field programmable logic arrays (FPGAs) or programmable array logics are nowadays introducing a new design paradigm over the possible techniques an electronic or computing designer may choose to make the desired hardware chip running. Thanks to the higher design flexibility and the increasing performances supported by these devices on several aspects such as power, frequency, and dependability, programmable logic devices design tools play a central rule among the computer aided design (CAD) tools available. The basic concept behind this success is the possibility of defining the logic functionality of an electronic circuits without having a direct interface with the silicon layout mask of the chip itself. FPGA CAD tools have an increasing impact on the performances offered by current programmable devices. state‐of‐the‐art CAD tools support both the synthesis of optimized logic functions and the implementation of design referring to the manner in which programmable switches and hard‐wired interconnections are placed between logic functions. In this article survey of the CAD tools for the programmable devices design phases is presented exploring the variety and particularity offered and analyzing the most influcnt results achieved on this area.

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A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Cited by 135 publications

References 22 publications

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

FPGAPALDesign Tools

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