A New RSA Encryption Architecture and Hardware Implementation based on Optimized Montgomery Multiplication

Fast exponentiation based on common-multiplicand-multiplication and minimal-signed-digit techniques

“…Therefore, we can have those operations concurrently executed for the two signed-digit segments. Furthermore, we can have the proposed improved MSD-CMM algorithm work more efficiently over signeddigit recoding arithmetic in massively parallel computing design for cryptographic hardware implementation [24].…”

Differential Power Analysis resistant hardware implementation of the RSA cryptosystem

“…When implemented on Xilinx XC2V4000 for k = 1024 , the maximum frequency achieved becomes 129.05 MHz; the total time 7.95 μs, and the throughput rate 128.80 Mb/s. As shown in Table 1, the resulting throughput rates are faster than [21,22,23], and almost the same speed as [24], which are also architectures using CSAs to realize Montgomery multipliers. Addition with CRPA takes k/w clock cycles, where k is the key length and w is the word length of CRPA.…”

Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture

“…Therefore, this modular multiplication algorithm is timeconsuming algorithm [11,17]. To further improve the performance of Montgomery modular multiplication algorithm, several computational techniques and hardware implementation have been proposed such as [7,9,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27 ]. One of the efficient modular multiplication algorithms is KPartition Montgomery Modular Multiplication (KPM3) algorithm [7].…”

“…Although hardware implementation of the binary Montgomery modular multiplication is simple, but it is time-consuming operation. To improve the performance of Montgomery modular multiplication algorithm and architecture, several hardware implementation method and computational techniques have been developed that can be categories into four groups: using high-radix technique [11][12][13][14][15][16][17], using systolic array architecture [18][19][20], using carry-save addition architecture [11,16,21,22,23], and using scalable architecture [9,12,24,25,26,27].…”