A New Single-chip Video Signal-processing LSI For The High-band 8mm Camcorder

Yamaguchi, Futao; Sato, K.; Takayanagi, Yoshiyuki; Nakaguchi, Masatoshi; Hirose, Hideki; Yoshioka, O.

doi:10.1109/icce.1993.697592

Cited by 4 publications

(1 citation statement)

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“…Due t o the ever increasing functional density of ICs, it is common for manufacturers t o place a large portion of analog processing on chip [2,3]. The difficulties of testing such systems arises from the limited observability and controllability of internal circuit structures, along with the non-linear effect that analog faults may cause on a circuit [4,5,6].…”

Section: : Introductionmentioning

confidence: 99%

On the testability of CMOS feedback amplifiers

Bishop

Ivanov²

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to simulate the faulty response of the opamp circuits. OUT method relies on repeated Monte Carlo fault simulations to examine differences in a circuit's response for each possible fault condition. A sine wave is used for the test stimulus in each case. FOUT closed loop configurations are considered for the study: integrator, differentiator, inverting amplifier, and comparator. w e tally the percentage of stuck-at, short, and open faults that are detectable with the feedback applied to demonstrate that the four feedback network configurations have little effect on the catastrophic fault coverage, as compared with similar tests performed for an open-loop configuration [I].

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