A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes

Hsieh, Yi-Bin; Kao, Yao-Huang

doi:10.1109/cicc.2007.4405737

Cited by 9 publications

(7 citation statements)

References 13 publications

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“…As summarized in Table 1, its EMI was reduced by 10.0 dB, its power consumption was 18 mW, and its settling-time was less than 4 s; the latter had been unachievable with previous SSCGs that applied to the SATA specifications [2][3][4][5][6]. Figure 26 shows a chip microphotograph.…”

Section: Measurement Resultsmentioning

confidence: 94%

“…However, their output jitter is still large because their digitally controlled ring oscillators generate large jitter and it is difficult to operate them accurately if there are PVT variations. The capacitance multiplication technique has been presented to reduce the design area as an approach in which the operation is based on that of a conventional SSCG [2,7,20]. However, the settling time is necessarily long because the loop bandwidth is set to be narrow.…”

Section: Introductionmentioning

confidence: 99%

“…The VCO frequency is thus modulated by the triangular wave. This SSCG can reduce EMI more substantially than other SSCGs because the linearity of the modulation can be obtained accurately by utilizing the logic circuits [2][3][4][5][6][7]. This SSCG has two main jitter sources.…”

Section: Introductionmentioning

confidence: 99%

“…The serialto-parallel converter (S/P) converts from the DATA to the received parallel data (RD) by using the CLK. In this SATA-PHY, the SSCG is applied a fractional SSCG because of a large EMI reduction [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The fractional SSCG should be narrow loop bandwidth because the quantized noise originated from a ΣΔ modulator is removed.…”

Section: Introductionmentioning

confidence: 99%

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A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

Kimura

Suzuki

Noto

2015

Journal of Electrical and Computer Engineering

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A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 s to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 m CMOS and achieves settling time of 3.91 s faster than 8.11 s of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 m and 18 mW, respectively.

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Section: Measurement Resultsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

Kimura

Suzuki

Noto

2015

Journal of Electrical and Computer Engineering

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“…The first method is to modulate the VCO control voltage directly [8]. The second method is to modulate the VCO phase [2].…”

Section: Introductionmentioning

confidence: 99%

A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

Chiueh

Juang

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. This research propose a SSCG using a ring voltagecontrolled oscillators (Ring-VCO) at 6GHz operating frequency; By using the proposed Ring-VCO, the active area of SSCG is 65% of comparable LC tank implementations, and Ring-VCO is much easier to characterized for any CMOS process. In addition, a multi-stage-noise-shaping (MASH) delta-sigma modulator (ΔΣ modulator) is used to reduce fractional spurs and quantization error for high EMI reduction. The chip is designed in TSMC 0.18um 1P6M CMOS process with active area of 500um×300um, and the simulation results consumes 60.43mW with 1.8V supply. The peak-to-peak jitter at 6GHz output of non spread-spectrum is 6.16ps, and the EMI reduction is 22.49dB with 5000ppm down spread to 5.97GHz.

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A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications

Alsuraisry¹,

Cheng

Jian

et al. 2017

Micro & Optical Tech Letters

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In this letter, a 6-GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA-III) applications in 0.18pm CMOS technology is presented. The 3rd-order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second-order delta-sigma (DR) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30-MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm 2 .

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A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes

Cited by 9 publications

References 13 publications

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications

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