A new technique for estimating lower bounds on latency for high level synthesis

Peixoto, H.P.; Jacome, Margarida F.

doi:10.1145/330855.331020

Cited by 6 publications

(3 citation statements)

References 4 publications

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“…This algorithm runs in time O(|P (v)| 2 ) in the worst case. The underlying methodology is quite similar to another lower bounding technique called tighter ASAP presented in [23]. In fact, the algorithm can quite easily be improved by using the distances d p,v of predecessors p ∈ P (v) as a second criterion to break ties such that whenever multiple predecessors of v have the same lower bound, one with the smallest distance to v will be processed first.…”

Section: Improved Bounds On Issue Cycles By Smart Countingmentioning

confidence: 99%

An integer programming approach to optimal basic block instruction scheduling for single-issue processors

Jünger

Mallach

2016

Discrete Optimization

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We present a novel integer programming formulation for basic block instruction scheduling on single-issue processors. The problem can be considered as a very general sequential task scheduling problem with delayed precedence-constraints. Our model is based on the linear ordering problem and has, in contrast to the last IP model proposed, numbers of variables and constraints that are strongly polynomial in the instance size. Combined with improved preprocessing techniques and given a time limit of ten minutes of CPU and system time, our branch-and-cut implementation is capable to solve all but eleven of the 369, 861 basic blocks of the SPEC 2000 integer and floating point benchmarks to proven optimality. This is competitive to the current state-of-the art constraint programming approach that has also been evaluated on this test suite.

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Section: Improved Bounds On Issue Cycles By Smart Countingmentioning

confidence: 99%

An integer programming approach to optimal basic block instruction scheduling for single-issue processors

Jünger

Mallach

2016

Discrete Optimization

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“…The second difference is that our ASAP M and ALAP M algorithms also identify scheduling steps with zero available resources, and remove them from the operation's time frame. Finally, the third difference is that, when the input graph is feed-forward (i.e., contains no SCC's), we use the TASAP algorithm proposed in [11], in order to obtain tighter bounds on the ASAP and ALAP scheduling times of the nodes. The use of the TASAP algorithm reduces the execution time of RS-FDRA by eliminating impossible execution steps from the operations' time frames.…”

Section: Schedulermentioning

confidence: 99%

Rs-Fdra

Akturan

Jacome

2001

Proceedings of the Ninth International Symposium on Hardware/Software Codesign - CODES '01

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The paper proposes a novel soflware-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RS-FDRA), suitable for optimizing compilers targeting embedded VLIW processors. The key difference between RS-FDRA and previous approaches is that our algorithm can handle code size constraints along with latency and resource constraints. This capability enables the exploration of pareto "optimal" points with respect to code size and performance. RS-FDRA can also minimize the increase in "register pressure" typically incurred by software pipelining. This ability is critical since, the need to insert spill code may result in significant performance degradation. Extensive experimental results are presented demonstrating that the extended set of optimization goals and constraints supported by RS-FDRA enables a thorough compiler-assisted exploration of Wade-offs among performance, code size, and register requirements, for time critical segments of embedded software components.

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“…Based on a behavioral description, a highlevel-synthesis system determines an allocation of resources, assignment of operations to resources, and a schedule for operations in an attempt to satisfy the design specifications and minimize some combination of delay, area, and power consumption [6]- [17]. Recently, in order to improve design area or performance estimation, researchers have considered the impact of physical details, e.g., floorplanning information, on high-level synthesis [18]- [23].…”

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confidence: 99%

Unified Incremental Physical-Level and High-Level Synthesis

Wang

Dick

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72× and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-levelsynthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.Index Terms-Behavioral synthesis, floorplanning, low power design.

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A new technique for estimating lower bounds on latency for high level synthesis

Cited by 6 publications

References 4 publications

An integer programming approach to optimal basic block instruction scheduling for single-issue processors

An integer programming approach to optimal basic block instruction scheduling for single-issue processors

Rs-Fdra

Unified Incremental Physical-Level and High-Level Synthesis

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