A new time-based architecture for serial communication links

Rashdan, M.; Yousif, Adil; Haslett, J.W.; Maundy, Brent

doi:10.1109/icecs.2009.5410875

Cited by 18 publications

(30 citation statements)

References 5 publications

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“…A time-based PPM-TDC architecture has been proposed by the authors in [10,11] and is shown in Fig. 1(a).…”

Section: Dts Architecturementioning

confidence: 99%

“…Modulating both the rising and the falling edges of the input clock signal allows more bits to be transmitted than can be transmitted by modulating one edge over the total time budget as in the PPM-TDC link [10]. To illustrate, assume that for a time budget T b , in order to use two modulation schemes, the number of transmitted bits N1 and N2 can be calculated as follows:…”

Section: Time Budgetmentioning

confidence: 99%

“…Note that by using the time budget T b for only one modulation scheme, the total number of transmitted bits is found to be [10]:…”

Section: Time Budgetmentioning

confidence: 99%

“…In order to transmit 8 bits using the PPM-TDC architecture proposed in [10] using the same input clock frequency, the required link resolution τ would be t ¼ T =2 2 N ¼ 3:9ps [10]. The PPM-TDC link resolution is very small compared to the 40 ps link resolution in the DTS architecture.…”

Section: Time Budgetmentioning

confidence: 99%

“…In [10,11], the authors introduced a low power serial link using a PPM scheme as a time-based link. In this paper, a new time-based high-speed link architecture is proposed.…”

Section: Introductionmentioning

confidence: 99%

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Differential Time Signaling Data-Link Architecture

Rashdan

Yousif

Haslett

et al. 2012

J Sign Process Syst

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A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.

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“…A time-based PPM-TDC architecture has been proposed by the authors in [10,11] and is shown in Fig. 1(a).…”

Section: Dts Architecturementioning

confidence: 99%

Section: Time Budgetmentioning

confidence: 99%

“…Note that by using the time budget T b for only one modulation scheme, the total number of transmitted bits is found to be [10]:…”

Section: Time Budgetmentioning

confidence: 99%

Section: Time Budgetmentioning

confidence: 99%

“…In [10,11], the authors introduced a low power serial link using a PPM scheme as a time-based link. In this paper, a new time-based high-speed link architecture is proposed.…”

Section: Introductionmentioning

confidence: 99%

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