2014 IEEE International Symposium on Circuits and Systems (ISCAS) 2014
DOI: 10.1109/iscas.2014.6865094
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A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry

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Cited by 4 publications
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“…Moreover, we found that the runtime of the two operators often dominates the overall runtime of LS optimization processes-accounts for approximately 79% of the overall runtime (see Appendix B.2.2). Thus, the runtime of the two operators acts as a bottleneck to the efficiency of LS, and inefficient LS may significantly increase the Time to Market [13], [14], [15], i.e., the overall duration for developing and commercializing new chips. Moreover, inefficient LS could significantly degrade the Quality of Results (see Section 6.4).…”
Section: Introductionmentioning
confidence: 99%
“…Moreover, we found that the runtime of the two operators often dominates the overall runtime of LS optimization processes-accounts for approximately 79% of the overall runtime (see Appendix B.2.2). Thus, the runtime of the two operators acts as a bottleneck to the efficiency of LS, and inefficient LS may significantly increase the Time to Market [13], [14], [15], i.e., the overall duration for developing and commercializing new chips. Moreover, inefficient LS could significantly degrade the Quality of Results (see Section 6.4).…”
Section: Introductionmentioning
confidence: 99%