A new wafer-level packaging technology for MEMS with hermetic micro-environment

Abstract

We report a new wafer-level packaging technology for miniature MEMS in a hermetic micro-environment. The unique and new feature of this technology is that it only uses low cost wafer-level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning steps as compared to more expensive process steps that will be required in other alternative wafer-level technologies involving thru-silicon vias or membrane lids. We have demonstrated this technology by packaging silicon-based AlN microsensors in packages of size 1.3 x 1.3 mm 2 and 200 micrometer thick. Our initial cost analysis has shown that when mass produced with high yields, this device will cost $0.10 to $0.90.The technology involves first preparing the lid and MEMS wafers separately with the sealring metal stack of Ti/Pt/Au on the MEMS wafers and Ti/Pt/Au/Ge/Au on the lid wafers. On the MEMS wafers, the Signal/Power/Ground interconnections to the wire-bond pads are isolated from the sealring metallization by an insulating AlN layer. Prior to bonding, the lid wafers were Bosch-etched in the wirebond pad area by 120 m and in the center hermetic device cavity area by 20 m. The MEMS and the lid wafers were then aligned and bonded in vacuum or in a nitrogen environment at or above the Au-Ge Eutectic temperature, 363 o C. The bonded wafers were then thinned and polished first on the MEMS side and then on the lid side. The MEMS side was thinned to 100 ms with a nearly scratch-free and crack-free surface. The lid side was similarly thinned to 100 ms exposing the wire-bond pads. After thinning, a 100 m thick lid remained over the MEMS features providing a 20 m high hermetic microenvironment. Thinned MEMS/Lid wafer-level assemblies were then sawed into individual devices. These devices can be integrated into the next-level assembly either by wire-bonding or by surface mounting.The wafer-level packaging approach developed in this project demonstrated RF Feedthroughs with <0.3 dB insertion loss and adequate RF performance through 2 GHz. Pressure monitoring Pirani structures built inside the hermetic lids have demonstrated the ability to detect leaks in the package. In our preliminary development experiments, we have demonstrated >50% hermetic yields. *Sandia is a multi-program laboratory operated by Sandia Corporation, a Lockheed Martin Company for the United States Department of Energy under contract DE-AC04-94AL85000. I. IntroductionRF MEMS resonators and switches allow miniaturization of RF systems by offering unique and compelling performance improvements in miniature volumes.The high-Q and miniature size of RF MEMS resonators provides the opportunity for substantial miniaturization of RF filters and frequency references. The low loss and low capacitance of RF MEMS switches offer improved adaptability and switching functions. However, to take advantage of these technologies over incumbent components, the technology's performance benefits must be maintained in a miniature volume. How these components are packaged and integrated play a cru...

Piezoelectric aluminum nitride thin films for microelectromechanical systems

“…Figure 6b shows the measured phase noise (a measurement of the oscillator short term frequency stability) of the single chip oscillator and specifi cations, converted to 532 MHz, frequency reference for the global system for mobile communications (GSM), a common standard for mobile phones. The AlN/ CMOS oscillator demonstrates communications grade phase noise performance, and when combined with separately developed thermal stabilization 40 and wafer level packaging 41 techniques, it is a viable technology for integration with RF electronics in next-generation military radios and wireless handsets. The process fl ow used to fabricate the AlN microresonator over CMOS is shown in Figure 7 .…”

Hermetic wafer-level packaging for RF MEMs: Effects on resonator performance

“…In the original reporting [2], a Ge-Au eutectic was used with the die wafer consisting of a metal stack of 20 nm of Ti / 100 nm of Pt / 500 nm of Au on AlN and the etched lid wafer consisting of a 20 nm of Ti / 100 nm of Pt / 440 nm of Au / 500 -700 nm of Ge / 100 nm of Au metal stack on the silicon lid substrate. Bonding was generally performed in the temperature range of 365-375 C for times ranging from 5 min to 15 min under 2-3 kN of pressure after an extended time, 20-30 minutes, at 320 C utilized for outgassing.…”

“…Microchemical analysis on the bonded interface indicated that the intended Ge-Au eutectic contained a large amount of Si. It is likely, given the lower bonding temperatures and times utilized for the microresonator assembly described earlier [2], that the eutectic alloy was mostly Si-Au eutectic where the silicon was introduced from the substrate. Due to the required elevated temperatures, bonding times, and increased difficulty using Ge, an aSi-Au eutectic was chosen.…”

“…Previous efforts in WLP have successfully demonstrated a cost effective integration scheme whereby a silicon lid wafer is bonded to an AlN resonator die wafer [2]. In this previously reported integration sequence, a lid wafer is fabricated by deep reactive ion etching (DRIE) of both a shallow and deep cavity into the silicon wafer.…”

Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

“…Packaging in the MEMS industry has the role of protecting the structures against the surrounding environment, including external shocks, dust, humidity, air damping, and other damaging elements [4]- [7]. Unlike ordinary devices, most MEMS devices with moving parts cannot be directly molded with engineering plastic and require unique packaging structures.…”